Программный i2c 1 МГц (для 16 МГц устройств) для AVR.

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Пт, 04/12/2020 - 14:49

Komandir

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Размер кода 138 байт.

Можно назначить SCL и SDA на любые выводы.

Пт, 04/12/2020 - 14:51

Komandir

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Для ASM:

001.equ        SCLPORT=PORTC
002.equ        SCLPIN=PORTC5
003.equ        SDAPORT=PORTC
004.equ        SDAPIN=PORTC4
005 
006.CSEG
007 
008.ORG        $0
009    RJMP    Start
010 
011.ORG        INT_VECTORS_SIZE
012;------------------------------
013i2c_init:
014    CBI SCLPORT-1,SCLPIN
015    CBI SDAPORT-1,SDAPIN
016    CBI SDAPORT,SDAPIN
017    CBI SCLPORT,SCLPIN
018    RET
019 
020;------------------------------
021i2c_start:
022    SBI SDAPORT-1,SDAPIN
023    RET
024 
025;------------------------------
026i2c_restart:
027    CBI SCLPORT-1,SCLPIN
028    CBI SCLPORT-1,SCLPIN
029    SBI SDAPORT-1,SDAPIN
030    RET
031 
032;------------------------------
033i2c_write:
034    LDI R25,8
035i2c_write_loop:
036    SBI SCLPORT-1,SCLPIN
037    SBRC    R24,7
038    CBI SDAPORT-1,SDAPIN
039    SBRS    R24,7
040    SBI SDAPORT-1,SDAPIN
041    ROL R24
042    CBI SCLPORT-1,SCLPIN
043i2c_write_loop1:
044    SBIS    SCLPORT-2,SCLPIN
045    RJMP    i2c_write_loop1
046    NOP
047    DEC R25
048    BRNE    i2c_write_loop
049    NOP
050    SBI SCLPORT-1,SCLPIN
051    CBI SDAPORT-1,SDAPIN
052    CBI SDAPORT-1,SDAPIN
053    CBI SDAPORT-1,SDAPIN
054    CBI SCLPORT-1,SCLPIN
055    CLR R24
056    SBIS    SDAPORT-2,SDAPIN
057    INC R24
058    CBI SCLPORT-1,SCLPIN
059    NOP
060    SBI SCLPORT-1,SCLPIN
061    RET
062 
063;------------------------------
064i2c_read:
065    LDI R25,8
066    BST R24,0
067i2c_read_loop:
068    SBI SCLPORT-1,SCLPIN
069    SBI SCLPORT-1,SCLPIN
070    SBI SCLPORT-1,SCLPIN
071    BLD R24,0
072    LSL R24
073    CBI SCLPORT-1,SCLPIN
074    SET
075    SBIS    SDAPORT-2,SDAPIN
076    CLT
077    DEC R25
078    BRNE    i2c_read_loop
079    BLD R24,0
080    SBI SCLPORT-1,SCLPIN
081    ROL R25
082    SBRS    R25,0
083    SBI SDAPORT-1,SDAPIN
084    SBRC    R25,0
085    CBI SDAPORT-1,SDAPIN
086    CBI SCLPORT-1,SCLPIN
087    CBI SCLPORT-1,SCLPIN
088    CBI SCLPORT-1,SCLPIN
089    CBI SCLPORT-1,SCLPIN
090    SBI SCLPORT-1,SCLPIN
091    CBI SDAPORT-1,SDAPIN
092    RET
093 
094;------------------------------
095i2c_stop:
096    SBI SDAPORT-1,SDAPIN
097    CBI SCLPORT-1,SCLPIN
098    CBI SCLPORT-1,SCLPIN
099    CBI SDAPORT-1,SDAPIN
100    RET
101 
102;------------------------------
103Start:
104    LDI R16,Low(RAMEND)
105    OUT SPL,R16
106    LDI R16,High(RAMEND)
107    OUT SPH,R16
108    CALL    i2c_init
109Loop:
110    CALL    i2c_start
111    LDI R24,$C0
112    CALL    i2c_write
113    LDI R24,$07
114    CALL    i2c_write
115    LDI R24,$FF
116    CALL    i2c_write
117    CALL    i2c_stop
118    CALL    i2c_start
119    LDI R24,$80
120    CALL    i2c_write
121    LDI R24,$03
122    CALL    i2c_write
123    LDI R24,$11
124    CALL    i2c_write
125    CALL    i2c_stop
126Loop1:
127    CALL    i2c_start
128    LDI R24,$80
129    CALL    i2c_write
130    LDI R24,$00
131    CALL    i2c_write
132    CALL    i2c_restart
133    LDI R24,$81
134    CALL    i2c_write
135    LDI R24,$01
136    CALL    i2c_read
137    CALL    i2c_stop
138    ANDI    R24,$01
139    BRNE    Loop1
140    CALL    i2c_start
141    LDI R24,$80
142    CALL    i2c_write
143    LDI R24,$01
144    CALL    i2c_write
145    CALL    i2c_restart
146    LDI R24,$81
147    CALL    i2c_write
148    LDI R24,$00
149    CALL    i2c_read
150    LDI R24,$01
151    CALL    i2c_read
152    CALL    i2c_stop
153    RJMP    Loop

Пт, 04/12/2020 - 14:54

Komandir

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Зарегистрирован: 18.08.2018

Для C++:

001#define SCLPORT PORTC
002#define SCLPIN PORTC5
003#define SDAPORT PORTC
004#define SDAPIN PORTC4
005void __attribute__ ((noinline)) i2c_init() {
006  asm volatile(
007    "CBI %0-1,%1\n\t"
008    "CBI %2-1,%3\n\t"
009    "CBI %2,%3\n\t"
010    "CBI %0,%1\n\t"
011    ::"I" (_SFR_IO_ADDR(SCLPORT)), "I" (SCLPIN), "I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN) 
012  );
013}
014void __attribute__ ((noinline)) i2c_start() {
015  asm volatile(
016    "SBI %0-1,%1\n\t"
017    ::"I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN)
018  );
019}
020void __attribute__ ((noinline)) i2c_restart() {
021  asm volatile(
022    "CBI %0-1,%1\n\t"
023    "CBI %0-1,%1\n\t"   //replacement for two NOP
024//    "NOP\n\t"
025//    "NOP\n\t"
026    "SBI %2-1,%3\n\t"
027    ::"I" (_SFR_IO_ADDR(SCLPORT)), "I" (SCLPIN), "I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN)
028  );
029}
030uint8_t __attribute__ ((noinline)) i2c_write(uint8_t data) {
031  uint8_t result;
032  uint8_t i=8;
033  asm  volatile(
034    "i2c_write_loop:"
035    "SBI %1-1,%2\n\t"
036    "SBRC %5,7\n\t"
037    "CBI %3-1,%4\n\t"
038    "SBRS %5,7\n\t"
039    "SBI %3-1,%4\n\t"
040    "ROL %5\n\t"
041    "CBI %1-1,%2\n\t"
042    "i2c_write_loop1:"
043    "SBIS %1-2,%2\n\t"
044    "RJMP i2c_write_loop1\n\t"
045    "NOP\n\t"
046    "DEC %6\n\t"
047    "BRNE i2c_write_loop\n\t"
048    "NOP\n\t"
049    "SBI %1-1,%2\n\t"
050    "CBI %3-1,%4\n\t"
051    "CBI %3-1,%4\n\t"   //replacement for two NOP
052    "CBI %3-1,%4\n\t"   //replacement for two NOP
053//    "NOP\n\t"
054//    "NOP\n\t"
055//    "NOP\n\t"
056//    "NOP\n\t"
057    "CBI %1-1,%2\n\t"
058    "CLR %0\n\t"
059    "SBIS %3-2,%4\n\t"
060    "INC %0\n\t"
061    "CBI %1-1,%2\n\t"   //replacement for two NOP
062//    "NOP\n\t"
063//    "NOP\n\t"
064    "NOP\n\t"
065    "SBI %1-1,%2\n\t"
066    : "=r" (result)
067    : "I" (_SFR_IO_ADDR(SCLPORT)), "I" (SCLPIN), "I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN), 
068      "r" (data), "r" (i)
069  );
070  return result;
071}
072uint8_t __attribute__ ((noinline)) i2c_read(uint8_t last=false) {
073  uint8_t result;
074  uint8_t i=8;
075  asm volatile(
076    "BST %0,0\n\t"
077    "i2c_read_loop:\n\t"
078    "SBI %1-1,%2\n\t"
079    "SBI %1-1,%2\n\t"   //replacement for two NOP
080    "SBI %1-1,%2\n\t"   //replacement for two NOP
081//    "NOP\n\t"
082//    "NOP\n\t"
083//    "NOP\n\t"
084//    "NOP\n\t"
085    "BLD %0,0\n\t"
086    "LSL %0\n\t"
087    "CBI %1-1,%2\n\t"
088    "SET\n\t"
089    "SBIS %3-2,%4\n\t"
090    "CLT\n\t"
091    "DEC %6\n\t"
092    "BRNE i2c_read_loop\n\t"
093    "BLD %0,0\n\t"
094    "SBI %1-1,%2\n\t"
095    "ROL %6\n\t"
096    "SBRS %6,0\n\t"
097    "SBI %3-1,%4\n\t"
098    "SBRC %6,0\n\t"
099    "CBI %3-1,%4\n\t"
100    "CBI %1-1,%2\n\t"
101    "CBI %1-1,%2\n\t"   //replacement for two NOP
102    "CBI %1-1,%2\n\t"   //replacement for two NOP
103    "CBI %1-1,%2\n\t"   //replacement for two NOP
104//    "NOP\n\t"
105//    "NOP\n\t"
106//    "NOP\n\t"
107//    "NOP\n\t"
108//    "NOP\n\t"
109//    "NOP\n\t"
110    "SBI %1-1,%2\n\t"
111    "CBI %3-1,%4\n\t"
112    : "=r" (result)
113    : "I" (_SFR_IO_ADDR(SCLPORT)), "I" (SCLPIN), "I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN), 
114      "r" (last), "r" (i)
115  );
116  return result;
117}
118void __attribute__ ((noinline)) i2c_stop() {
119  asm volatile(
120    "SBI %2-1,%3\n\t"
121    "CBI %0-1,%1\n\t"
122    "CBI %0-1,%1\n\t"   //replacement for two NOP
123//    "NOP\n\t"
124//    "NOP\n\t"
125    "CBI %2-1,%3\n\t"
126    ::"I" (_SFR_IO_ADDR(SCLPORT)), "I" (SCLPIN), "I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN)
127  );
128}
129 
130void setup() {
131  Serial.begin(9600);
132  i2c_init();
133}
134void loop() {
135uint8_t b,b1;
136  i2c_start();
137  i2c_write(0x40<<1);
138  i2c_write(0x03);
139  i2c_write(0x11);
140  i2c_stop();
141  do {
142    i2c_start();
143    i2c_write(0x40<<1);
144    i2c_write(0x00);
145    i2c_restart();
146    i2c_write(0x40<<1 | 0x01);
147    b=i2c_read(true);
148    i2c_stop();
149  } while (b & 0x01);
150  i2c_start();
151  i2c_write(0x40<<1);
152  i2c_write(0x01);
153  i2c_restart();
154  i2c_write(0x40<<1 | 0x01);
155  b=i2c_read(false);
156  b1=i2c_read(true);
157  i2c_stop();
158  Serial.print(b, HEX);
159  Serial.print(" ");
160  Serial.println(b1, HEX);
161  delay(1000);
162  delay(100);
163}

Пт, 04/12/2020 - 15:00

Komandir

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Помимо самих функций для интерфейса i2c - код содержит примеры, для схемы:

Пт, 04/12/2020 - 15:17

Komandir

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Зарегистрирован: 18.08.2018

В железе тестировал на OLED 128x32 SSD1306. Код для него ещё короче, так как не нужны функции i2c_restart и i2c_read.

192 кадра в секунду !!!

Пт, 04/12/2020 - 17:18

andriano

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1 000 000 / 1024 / 192 = 5,0862630208333333333333333333333

Т.е. Вы передаете байт за 5 тактов?

Можно привести исходник, который можно было бы "пощупать"?

Прошу прощения, не обратил внимания, что х32, а не х64, тогда 96 кадров для х64 - все сходится.

Но просьба насчет исходника остается.

Ср, 29/03/2023 - 09:39

Komandir

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Вот код для для SSD1306 128x32:

001#define SCLPORT PORTC
002#define SCLPIN PORTC5
003#define SDAPORT PORTC
004#define SDAPIN PORTC4
005#include <avr/pgmspace.h>
006 
007void __attribute__ ((noinline)) i2c_init() {
008  asm volatile(
009    "CBI %0-1,%1\n\t"
010    "CBI %2-1,%3\n\t"
011    "CBI %2,%3\n\t"
012    "CBI %0,%1\n\t"
013    ::"I" (_SFR_IO_ADDR(SCLPORT)), "I" (SCLPIN), "I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN) 
014  );
015}
016 
017void __attribute__ ((noinline)) i2c_start() {
018  asm volatile(
019    "SBI %0-1,%1\n\t"
020    ::"I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN)
021  );
022}
023 
024uint8_t __attribute__ ((noinline)) i2c_write(uint8_t data) {
025  uint8_t result;
026  uint8_t i=8;
027  asm  volatile(
028    "i2c_write_loop:"
029    "SBI %1-1,%2\n\t"
030    "SBRC %5,7\n\t"
031    "CBI %3-1,%4\n\t"
032    "SBRS %5,7\n\t"
033    "SBI %3-1,%4\n\t"
034    "ROL %5\n\t"
035    "CBI %1-1,%2\n\t"
036    "i2c_write_loop1:"
037    "SBIS %1-2,%2\n\t"
038    "RJMP i2c_write_loop1\n\t"
039    "NOP\n\t"
040    "DEC %6\n\t"
041    "BRNE i2c_write_loop\n\t"
042    "NOP\n\t"
043    "SBI %1-1,%2\n\t"
044    "CBI %3-1,%4\n\t"
045    "CBI %3-1,%4\n\t"   //replacement for two NOP
046    "CBI %3-1,%4\n\t"   //replacement for two NOP
047//    "NOP\n\t"
048//    "NOP\n\t"
049//    "NOP\n\t"
050//    "NOP\n\t"
051    "CBI %1-1,%2\n\t"
052    "CLR %0\n\t"
053    "SBIS %3-2,%4\n\t"
054    "INC %0\n\t"
055    "CBI %1-1,%2\n\t"   //replacement for two NOP
056//    "NOP\n\t"
057//    "NOP\n\t"
058    "NOP\n\t"
059    "SBI %1-1,%2\n\t"
060    : "=r" (result)
061    : "I" (_SFR_IO_ADDR(SCLPORT)), "I" (SCLPIN), "I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN), 
062      "r" (data), "r" (i)
063  );
064  return result;
065}
066 
067void __attribute__ ((noinline)) i2c_stop() {
068  asm volatile(
069    "SBI %2-1,%3\n\t"
070    "CBI %0-1,%1\n\t"
071    "CBI %0-1,%1\n\t"   //replacement for two NOP
072//    "NOP\n\t"
073//    "NOP\n\t"
074    "CBI %2-1,%3\n\t"
075    ::"I" (_SFR_IO_ADDR(SCLPORT)), "I" (SCLPIN), "I" (_SFR_IO_ADDR(SDAPORT)), "I" (SDAPIN)
076  );
077}
078 
079static const uint8_t PROGMEM init_bytes[]={0x3C<<1,0x00,0xAE,0xD5,0x80,0xA8,0x1F,0xD3,0x00,0x40,0x8D,0x14,0x20,0x00,0xA0,0xC0,
080                                                   0xDA,0x02,0xD9,0xF1,0xDB,0x40,0x21,0x00,0x7f,0x22,0x00,0x03,0xA4,0xA6,0xAF};
081static const uint8_t PROGMEM impreza[] = {
0820xF8, 0xF8, 0x00, 0x00, 0xF8, 0xF8, 0x38, 0x70, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
0830x80, 0xC0, 0xE0, 0x70, 0x38, 0xF8, 0xF8, 0x00, 0x00, 0xF8, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18,
0840x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38, 0xF0, 0xE0, 0x00, 0x00, 0xF8, 0xF8,
0850x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38, 0xF0,
0860xE0, 0x00, 0x00, 0xE0, 0xF0, 0x38, 0x18, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
0870x98, 0x98, 0x98, 0x98, 0x98, 0x98, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
0880x18, 0x98, 0x98, 0xD8, 0xD8, 0x78, 0x78, 0x38, 0x38, 0x18, 0x18, 0x00, 0x00, 0xE0, 0xF0, 0x38,
0890x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38, 0xF0, 0xE0,
0900x1F, 0x1F, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x01, 0x03, 0x07, 0x0E, 0x1C, 0x0E, 0x07,
0910x03, 0x01, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x06, 0x06, 0x06,
0920x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x07, 0x03, 0x01, 0x00, 0x00, 0x1F, 0x1F,
0930x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x0E, 0x1F, 0x1B,
0940x11, 0x00, 0x00, 0x07, 0x0F, 0x1C, 0x18, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
0950x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x00, 0x00, 0x18, 0x18, 0x1C, 0x1C, 0x1E, 0x1E, 0x1B, 0x1B,
096 
0970x19, 0x19, 0x19, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x1F, 0x1F, 0x00,
0980x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1F, 0x1F};
099void setup() {
100  i2c_init();
101  i2c_start();
102  for(uint8_t i=0;i<sizeof(init_bytes);i++) i2c_write(pgm_read_byte(init_bytes+i));
103  i2c_stop();
104  i2c_start();
105  i2c_write(0x3C<<1);
106  i2c_write(0x40);
107}
108void loop() {
109  for(uint8_t i=0;i<=127;i++) i2c_write(0x00);
110  for(uint16_t i=0;i<=255;i++) i2c_write(pgm_read_byte(impreza+i));
111  for(uint8_t i=0;i<=127;i++) i2c_write(0x00);
112  while (1) {};
113}

Пт, 04/12/2020 - 20:31

andriano

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Это софтверный I2C на стандартных хардверных ногах?

Пт, 04/12/2020 - 20:31

DetSimen

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Komandir пишет:

Для ASM:

equ        SCLPORT=PORTC
equ        SCLPIN=PORTC5
equ        SDAPORT=PORTC
equ        SDAPIN=PORTC

Снимаю шляпу. :-)

Пт, 04/12/2020 - 20:33

Komandir

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Ноги можно прописать любые в самом начале ...

Пт, 04/12/2020 - 20:35

#10

-NMi-

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Зарегистрирован: 20.08.2018

`1`	`.equ SCLPORT=PORTC`

`2`	`.equ SCLPIN=PORTC5`

`3`	`.equ SDAPORT=PORTC`

.equ SDAPIN=PORTC

`4`	А как это работает???

Пт, 04/12/2020 - 20:43

#11

Komandir

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Пропишите те порты и пины, где у Вас живет i2c девайс и компилируйте/заливайте/тестируйте ...

Пт, 04/12/2020 - 20:43

#12

-NMi-

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Зарегистрирован: 20.08.2018

Эти alias-ы реально переключают порт(ы) со входа на выход и наоборот???

Просто я не понимаю, как это работает.

Пт, 04/12/2020 - 20:52

#13

Komandir

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Нет. Они используются дальше в командах - пример CBI SCLPORT-1,SCLPIN

Макроподстановка однако ...

Пт, 04/12/2020 - 20:55

#14

ua6em

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Зарегистрирован: 17.08.2016

Нижнюю строчку поправь, а то галиматья получается

.equ SDAPIN=PORTC4

Пт, 04/12/2020 - 20:58

#15

Komandir

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ua6em пишет:

Нижнюю строчку поправь, а то галиматья получается

.equ SDAPIN=PORTC4

У меня то вроде всё четко ...

Пт, 04/12/2020 - 21:06

#16

-NMi-

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SBI - поставим бит в порту

CBI - сбросим (абнулим) бит в порту.

Это понятно, зачем ЧЕТЫРЕ алиаса?????????????

Пт, 04/12/2020 - 21:09

#17

Komandir

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Зарегистрирован: 18.08.2018

Две пары ПОРТ + ПИН

Пт, 04/12/2020 - 21:17

#18

-NMi-

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Зарегистрирован: 20.08.2018

Есть возможность выложить РАЗДЭЗ ассемблерного кода? Реально не понятно, как софт работает с портами.

Ну или скомпиль в объектник, я сам раздезю и гляну.

Пт, 04/12/2020 - 21:26

#19

Komandir

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Зарегистрирован: 18.08.2018

0001AVRASM ver. 2.1.42  ..\main.asm Fri Dec 04 20:24:30 2020
0002 
0003[builtin](2): Including file 'C:\Program Files (x86)\Labcenter Electronics\Proteus 8 Professional\Tools\AVRASM\appnotes\m328Pdef.inc'
0004                  
0005                 .equ       SCLPORT=PORTC
0006                  
0007                 ;***** Created: 2010-02-25 11:46 ******* Source: ATmega328P.xml **********
0008                 ;*************************************************************************
0009                 ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
0010                 ;* 
0011                 ;* Number            : AVR000
0012                 ;* File Name         : "m328Pdef.inc"
0013                 ;* Title             : Register/Bit Definitions for the ATmega328P
0014                 ;* Date              : 2010-02-25
0015                 ;* Version           : 2.35
0016                 ;* Support E-mail    : <a href="mailto:avr@atmel.com">avr@atmel.com</a>
0017                 ;* Target MCU        : ATmega328P
0018                 ;* 
0019                 ;* DESCRIPTION
0020                 ;* When including this file in the assembly program file, all I/O register 
0021                 ;* names and I/O register bit names appearing in the data book can be used.
0022                 ;* In addition, the six registers forming the three data pointers X, Y and 
0023                 ;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
0024                 ;* SRAM is also defined 
0025                 ;* 
0026                 ;* The Register names are represented by their hexadecimal address.
0027                 ;* 
0028                 ;* The Register Bit names are represented by their bit number (0-7).
0029                 ;* 
0030                 ;* Please observe the difference in using the bit names with instructions
0031                 ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
0032                 ;* (skip if bit in register set/cleared). The following example illustrates
0033                 ;* this:
0034                 ;* 
0035                 ;* in    r16,PORTB             ;read PORTB latch
0036                 ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
0037                 ;* out   PORTB,r16             ;output to PORTB
0038                 ;* 
0039                 ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
0040                 ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
0041                 ;* rjmp  TOV0_is_set           ;jump if set
0042                 ;* ...                         ;otherwise do something else
0043                 ;*************************************************************************
0044                  
0045                 #ifndef _M328PDEF_INC_
0046                 #define _M328PDEF_INC_
0047                  
0048                  
0049                 #pragma partinc 0
0050                  
0051                 ; ***** SPECIFY DEVICE ***************************************************
0052                 .device ATmega328P
0053                 #pragma AVRPART ADMIN PART_NAME ATmega328P
0054                 .equ   SIGNATURE_000   = 0x1e
0055                 .equ   SIGNATURE_001   = 0x95
0056                 .equ   SIGNATURE_002   = 0x0f
0057                  
0058                 #pragma AVRPART CORE CORE_VERSION V2E
0059                  
0060                  
0061                 ; ***** I/O REGISTER DEFINITIONS *****************************************
0062                 ; NOTE:
0063                 ; Definitions marked "MEMORY MAPPED"are extended I/O ports
0064                 ; and cannot be used with IN/OUT instructions
0065                 .equ   UDR0    = 0xc6  ; MEMORY MAPPED
0066                 .equ   UBRR0L  = 0xc4  ; MEMORY MAPPED
0067                 .equ   UBRR0H  = 0xc5  ; MEMORY MAPPED
0068                 .equ   UCSR0C  = 0xc2  ; MEMORY MAPPED
0069                 .equ   UCSR0B  = 0xc1  ; MEMORY MAPPED
0070                 .equ   UCSR0A  = 0xc0  ; MEMORY MAPPED
0071                 .equ   TWAMR   = 0xbd  ; MEMORY MAPPED
0072                 .equ   TWCR    = 0xbc  ; MEMORY MAPPED
0073                 .equ   TWDR    = 0xbb  ; MEMORY MAPPED
0074                 .equ   TWAR    = 0xba  ; MEMORY MAPPED
0075                 .equ   TWSR    = 0xb9  ; MEMORY MAPPED
0076                 .equ   TWBR    = 0xb8  ; MEMORY MAPPED
0077                 .equ   ASSR    = 0xb6  ; MEMORY MAPPED
0078                 .equ   OCR2B   = 0xb4  ; MEMORY MAPPED
0079                 .equ   OCR2A   = 0xb3  ; MEMORY MAPPED
0080                 .equ   TCNT2   = 0xb2  ; MEMORY MAPPED
0081                 .equ   TCCR2B  = 0xb1  ; MEMORY MAPPED
0082                 .equ   TCCR2A  = 0xb0  ; MEMORY MAPPED
0083                 .equ   OCR1BL  = 0x8a  ; MEMORY MAPPED
0084                 .equ   OCR1BH  = 0x8b  ; MEMORY MAPPED
0085                 .equ   OCR1AL  = 0x88  ; MEMORY MAPPED
0086                 .equ   OCR1AH  = 0x89  ; MEMORY MAPPED
0087                 .equ   ICR1L   = 0x86  ; MEMORY MAPPED
0088                 .equ   ICR1H   = 0x87  ; MEMORY MAPPED
0089                 .equ   TCNT1L  = 0x84  ; MEMORY MAPPED
0090                 .equ   TCNT1H  = 0x85  ; MEMORY MAPPED
0091                 .equ   TCCR1C  = 0x82  ; MEMORY MAPPED
0092                 .equ   TCCR1B  = 0x81  ; MEMORY MAPPED
0093                 .equ   TCCR1A  = 0x80  ; MEMORY MAPPED
0094                 .equ   DIDR1   = 0x7f  ; MEMORY MAPPED
0095                 .equ   DIDR0   = 0x7e  ; MEMORY MAPPED
0096                 .equ   ADMUX   = 0x7c  ; MEMORY MAPPED
0097                 .equ   ADCSRB  = 0x7b  ; MEMORY MAPPED
0098                 .equ   ADCSRA  = 0x7a  ; MEMORY MAPPED
0099                 .equ   ADCH    = 0x79  ; MEMORY MAPPED
0100                 .equ   ADCL    = 0x78  ; MEMORY MAPPED
0101                 .equ   TIMSK2  = 0x70  ; MEMORY MAPPED
0102                 .equ   TIMSK1  = 0x6f  ; MEMORY MAPPED
0103                 .equ   TIMSK0  = 0x6e  ; MEMORY MAPPED
0104                 .equ   PCMSK1  = 0x6c  ; MEMORY MAPPED
0105                 .equ   PCMSK2  = 0x6d  ; MEMORY MAPPED
0106                 .equ   PCMSK0  = 0x6b  ; MEMORY MAPPED
0107                 .equ   EICRA   = 0x69  ; MEMORY MAPPED
0108                 .equ   PCICR   = 0x68  ; MEMORY MAPPED
0109                 .equ   OSCCAL  = 0x66  ; MEMORY MAPPED
0110                 .equ   PRR = 0x64  ; MEMORY MAPPED
0111                 .equ   CLKPR   = 0x61  ; MEMORY MAPPED
0112                 .equ   WDTCSR  = 0x60  ; MEMORY MAPPED
0113                 .equ   SREG    = 0x3f
0114                 .equ   SPL = 0x3d
0115                 .equ   SPH = 0x3e
0116                 .equ   SPMCSR  = 0x37
0117                 .equ   MCUCR   = 0x35
0118                 .equ   MCUSR   = 0x34
0119                 .equ   SMCR    = 0x33
0120                 .equ   ACSR    = 0x30
0121                 .equ   SPDR    = 0x2e
0122                 .equ   SPSR    = 0x2d
0123                 .equ   SPCR    = 0x2c
0124                 .equ   GPIOR2  = 0x2b
0125                 .equ   GPIOR1  = 0x2a
0126                 .equ   OCR0B   = 0x28
0127                 .equ   OCR0A   = 0x27
0128                 .equ   TCNT0   = 0x26
0129                 .equ   TCCR0B  = 0x25
0130                 .equ   TCCR0A  = 0x24
0131                 .equ   GTCCR   = 0x23
0132                 .equ   EEARH   = 0x22
0133                 .equ   EEARL   = 0x21
0134                 .equ   EEDR    = 0x20
0135                 .equ   EECR    = 0x1f
0136                 .equ   GPIOR0  = 0x1e
0137                 .equ   EIMSK   = 0x1d
0138                 .equ   EIFR    = 0x1c
0139                 .equ   PCIFR   = 0x1b
0140                 .equ   TIFR2   = 0x17
0141                 .equ   TIFR1   = 0x16
0142                 .equ   TIFR0   = 0x15
0143                 .equ   PORTD   = 0x0b
0144                 .equ   DDRD    = 0x0a
0145                 .equ   PIND    = 0x09
0146                 .equ   PORTC   = 0x08
0147                 .equ   DDRC    = 0x07
0148                 .equ   PINC    = 0x06
0149                 .equ   PORTB   = 0x05
0150                 .equ   DDRB    = 0x04
0151                 .equ   PINB    = 0x03
0152                  
0153                  
0154                 ; ***** BIT DEFINITIONS **************************************************
0155                  
0156                 ; ***** USART0 ***********************
0157                 ; UDR0 - USART I/O Data Register
0158                 .equ   UDR0_0  = 0 ; USART I/O Data Register bit 0
0159                 .equ   UDR0_1  = 1 ; USART I/O Data Register bit 1
0160                 .equ   UDR0_2  = 2 ; USART I/O Data Register bit 2
0161                 .equ   UDR0_3  = 3 ; USART I/O Data Register bit 3
0162                 .equ   UDR0_4  = 4 ; USART I/O Data Register bit 4
0163                 .equ   UDR0_5  = 5 ; USART I/O Data Register bit 5
0164                 .equ   UDR0_6  = 6 ; USART I/O Data Register bit 6
0165                 .equ   UDR0_7  = 7 ; USART I/O Data Register bit 7
0166                  
0167                 ; UCSR0A - USART Control and Status Register A
0168                 .equ   MPCM0   = 0 ; Multi-processor Communication Mode
0169                 .equ   U2X0    = 1 ; Double the USART transmission speed
0170                 .equ   UPE0    = 2 ; Parity Error
0171                 .equ   DOR0    = 3 ; Data overRun
0172                 .equ   FE0 = 4 ; Framing Error
0173                 .equ   UDRE0   = 5 ; USART Data Register Empty
0174                 .equ   TXC0    = 6 ; USART Transmitt Complete
0175                 .equ   RXC0    = 7 ; USART Receive Complete
0176                  
0177                 ; UCSR0B - USART Control and Status Register B
0178                 .equ   TXB80   = 0 ; Transmit Data Bit 8
0179                 .equ   RXB80   = 1 ; Receive Data Bit 8
0180                 .equ   UCSZ02  = 2 ; Character Size
0181                 .equ   TXEN0   = 3 ; Transmitter Enable
0182                 .equ   RXEN0   = 4 ; Receiver Enable
0183                 .equ   UDRIE0  = 5 ; USART Data register Empty Interrupt Enable
0184                 .equ   TXCIE0  = 6 ; TX Complete Interrupt Enable
0185                 .equ   RXCIE0  = 7 ; RX Complete Interrupt Enable
0186                  
0187                 ; UCSR0C - USART Control and Status Register C
0188                 .equ   UCPOL0  = 0 ; Clock Polarity
0189                 .equ   UCSZ00  = 1 ; Character Size
0190                 .equ   UCPHA0  = UCSZ00    ; For compatibility
0191                 .equ   UCSZ01  = 2 ; Character Size
0192                 .equ   UDORD0  = UCSZ01    ; For compatibility
0193                 .equ   USBS0   = 3 ; Stop Bit Select
0194                 .equ   UPM00   = 4 ; Parity Mode Bit 0
0195                 .equ   UPM01   = 5 ; Parity Mode Bit 1
0196                 .equ   UMSEL00 = 6 ; USART Mode Select
0197                 .equ   UMSEL0  = UMSEL00   ; For compatibility
0198                 .equ   UMSEL01 = 7 ; USART Mode Select
0199                 .equ   UMSEL1  = UMSEL01   ; For compatibility
0200                  
0201                 ; UBRR0H - USART Baud Rate Register High Byte
0202                 .equ   UBRR8   = 0 ; USART Baud Rate Register bit 8
0203                 .equ   UBRR9   = 1 ; USART Baud Rate Register bit 9
0204                 .equ   UBRR10  = 2 ; USART Baud Rate Register bit 10
0205                 .equ   UBRR11  = 3 ; USART Baud Rate Register bit 11
0206                  
0207                 ; UBRR0L - USART Baud Rate Register Low Byte
0208                 .equ   _UBRR0  = 0 ; USART Baud Rate Register bit 0
0209                 .equ   _UBRR1  = 1 ; USART Baud Rate Register bit 1
0210                 .equ   UBRR2   = 2 ; USART Baud Rate Register bit 2
0211                 .equ   UBRR3   = 3 ; USART Baud Rate Register bit 3
0212                 .equ   UBRR4   = 4 ; USART Baud Rate Register bit 4
0213                 .equ   UBRR5   = 5 ; USART Baud Rate Register bit 5
0214                 .equ   UBRR6   = 6 ; USART Baud Rate Register bit 6
0215                 .equ   UBRR7   = 7 ; USART Baud Rate Register bit 7
0216                  
0217                  
0218                 ; ***** TWI **************************
0219                 ; TWAMR - TWI (Slave) Address Mask Register
0220                 .equ   TWAM0   = 1 ; 
0221                 .equ   TWAMR0  = TWAM0 ; For compatibility
0222                 .equ   TWAM1   = 2 ; 
0223                 .equ   TWAMR1  = TWAM1 ; For compatibility
0224                 .equ   TWAM2   = 3 ; 
0225                 .equ   TWAMR2  = TWAM2 ; For compatibility
0226                 .equ   TWAM3   = 4 ; 
0227                 .equ   TWAMR3  = TWAM3 ; For compatibility
0228                 .equ   TWAM4   = 5 ; 
0229                 .equ   TWAMR4  = TWAM4 ; For compatibility
0230                 .equ   TWAM5   = 6 ; 
0231                 .equ   TWAMR5  = TWAM5 ; For compatibility
0232                 .equ   TWAM6   = 7 ; 
0233                 .equ   TWAMR6  = TWAM6 ; For compatibility
0234                  
0235                 ; TWBR - TWI Bit Rate register
0236                 .equ   TWBR0   = 0 ; 
0237                 .equ   TWBR1   = 1 ; 
0238                 .equ   TWBR2   = 2 ; 
0239                 .equ   TWBR3   = 3 ; 
0240                 .equ   TWBR4   = 4 ; 
0241                 .equ   TWBR5   = 5 ; 
0242                 .equ   TWBR6   = 6 ; 
0243                 .equ   TWBR7   = 7 ; 
0244                  
0245                 ; TWCR - TWI Control Register
0246                 .equ   TWIE    = 0 ; TWI Interrupt Enable
0247                 .equ   TWEN    = 2 ; TWI Enable Bit
0248                 .equ   TWWC    = 3 ; TWI Write Collition Flag
0249                 .equ   TWSTO   = 4 ; TWI Stop Condition Bit
0250                 .equ   TWSTA   = 5 ; TWI Start Condition Bit
0251                 .equ   TWEA    = 6 ; TWI Enable Acknowledge Bit
0252                 .equ   TWINT   = 7 ; TWI Interrupt Flag
0253                  
0254                 ; TWSR - TWI Status Register
0255                 .equ   TWPS0   = 0 ; TWI Prescaler
0256                 .equ   TWPS1   = 1 ; TWI Prescaler
0257                 .equ   TWS3    = 3 ; TWI Status
0258                 .equ   TWS4    = 4 ; TWI Status
0259                 .equ   TWS5    = 5 ; TWI Status
0260                 .equ   TWS6    = 6 ; TWI Status
0261                 .equ   TWS7    = 7 ; TWI Status
0262                  
0263                 ; TWDR - TWI Data register
0264                 .equ   TWD0    = 0 ; TWI Data Register Bit 0
0265                 .equ   TWD1    = 1 ; TWI Data Register Bit 1
0266                 .equ   TWD2    = 2 ; TWI Data Register Bit 2
0267                 .equ   TWD3    = 3 ; TWI Data Register Bit 3
0268                 .equ   TWD4    = 4 ; TWI Data Register Bit 4
0269                 .equ   TWD5    = 5 ; TWI Data Register Bit 5
0270                 .equ   TWD6    = 6 ; TWI Data Register Bit 6
0271                 .equ   TWD7    = 7 ; TWI Data Register Bit 7
0272                  
0273                 ; TWAR - TWI (Slave) Address register
0274                 .equ   TWGCE   = 0 ; TWI General Call Recognition Enable Bit
0275                 .equ   TWA0    = 1 ; TWI (Slave) Address register Bit 0
0276                 .equ   TWA1    = 2 ; TWI (Slave) Address register Bit 1
0277                 .equ   TWA2    = 3 ; TWI (Slave) Address register Bit 2
0278                 .equ   TWA3    = 4 ; TWI (Slave) Address register Bit 3
0279                 .equ   TWA4    = 5 ; TWI (Slave) Address register Bit 4
0280                 .equ   TWA5    = 6 ; TWI (Slave) Address register Bit 5
0281                 .equ   TWA6    = 7 ; TWI (Slave) Address register Bit 6
0282                  
0283                  
0284                 ; ***** TIMER_COUNTER_1 **************
0285                 ; TIMSK1 - Timer/Counter Interrupt Mask Register
0286                 .equ   TOIE1   = 0 ; Timer/Counter1 Overflow Interrupt Enable
0287                 .equ   OCIE1A  = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable
0288                 .equ   OCIE1B  = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable
0289                 .equ   ICIE1   = 5 ; Timer/Counter1 Input Capture Interrupt Enable
0290                  
0291                 ; TIFR1 - Timer/Counter Interrupt Flag register
0292                 .equ   TOV1    = 0 ; Timer/Counter1 Overflow Flag
0293                 .equ   OCF1A   = 1 ; Output Compare Flag 1A
0294                 .equ   OCF1B   = 2 ; Output Compare Flag 1B
0295                 .equ   ICF1    = 5 ; Input Capture Flag 1
0296                  
0297                 ; TCCR1A - Timer/Counter1 Control Register A
0298                 .equ   WGM10   = 0 ; Waveform Generation Mode
0299                 .equ   WGM11   = 1 ; Waveform Generation Mode
0300                 .equ   COM1B0  = 4 ; Compare Output Mode 1B, bit 0
0301                 .equ   COM1B1  = 5 ; Compare Output Mode 1B, bit 1
0302                 .equ   COM1A0  = 6 ; Comparet Ouput Mode 1A, bit 0
0303                 .equ   COM1A1  = 7 ; Compare Output Mode 1A, bit 1
0304                  
0305                 ; TCCR1B - Timer/Counter1 Control Register B
0306                 .equ   CS10    = 0 ; Prescaler source of Timer/Counter 1
0307                 .equ   CS11    = 1 ; Prescaler source of Timer/Counter 1
0308                 .equ   CS12    = 2 ; Prescaler source of Timer/Counter 1
0309                 .equ   WGM12   = 3 ; Waveform Generation Mode
0310                 .equ   WGM13   = 4 ; Waveform Generation Mode
0311                 .equ   ICES1   = 6 ; Input Capture 1 Edge Select
0312                 .equ   ICNC1   = 7 ; Input Capture 1 Noise Canceler
0313                  
0314                 ; TCCR1C - Timer/Counter1 Control Register C
0315                 .equ   FOC1B   = 6 ; 
0316                 .equ   FOC1A   = 7 ; 
0317                  
0318                 ; GTCCR - General Timer/Counter Control Register
0319                 .equ   PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
0320                 .equ   TSM = 7 ; Timer/Counter Synchronization Mode
0321                  
0322                  
0323                 ; ***** TIMER_COUNTER_2 **************
0324                 ; TIMSK2 - Timer/Counter Interrupt Mask register
0325                 .equ   TOIE2   = 0 ; Timer/Counter2 Overflow Interrupt Enable
0326                 .equ   TOIE2A  = TOIE2 ; For compatibility
0327                 .equ   OCIE2A  = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable
0328                 .equ   OCIE2B  = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable
0329                  
0330                 ; TIFR2 - Timer/Counter Interrupt Flag Register
0331                 .equ   TOV2    = 0 ; Timer/Counter2 Overflow Flag
0332                 .equ   OCF2A   = 1 ; Output Compare Flag 2A
0333                 .equ   OCF2B   = 2 ; Output Compare Flag 2B
0334                  
0335                 ; TCCR2A - Timer/Counter2 Control Register A
0336                 .equ   WGM20   = 0 ; Waveform Genration Mode
0337                 .equ   WGM21   = 1 ; Waveform Genration Mode
0338                 .equ   COM2B0  = 4 ; Compare Output Mode bit 0
0339                 .equ   COM2B1  = 5 ; Compare Output Mode bit 1
0340                 .equ   COM2A0  = 6 ; Compare Output Mode bit 1
0341                 .equ   COM2A1  = 7 ; Compare Output Mode bit 1
0342                  
0343                 ; TCCR2B - Timer/Counter2 Control Register B
0344                 .equ   CS20    = 0 ; Clock Select bit 0
0345                 .equ   CS21    = 1 ; Clock Select bit 1
0346                 .equ   CS22    = 2 ; Clock Select bit 2
0347                 .equ   WGM22   = 3 ; Waveform Generation Mode
0348                 .equ   FOC2B   = 6 ; Force Output Compare B
0349                 .equ   FOC2A   = 7 ; Force Output Compare A
0350                  
0351                 ; TCNT2 - Timer/Counter2
0352                 .equ   TCNT2_0 = 0 ; Timer/Counter 2 bit 0
0353                 .equ   TCNT2_1 = 1 ; Timer/Counter 2 bit 1
0354                 .equ   TCNT2_2 = 2 ; Timer/Counter 2 bit 2
0355                 .equ   TCNT2_3 = 3 ; Timer/Counter 2 bit 3
0356                 .equ   TCNT2_4 = 4 ; Timer/Counter 2 bit 4
0357                 .equ   TCNT2_5 = 5 ; Timer/Counter 2 bit 5
0358                 .equ   TCNT2_6 = 6 ; Timer/Counter 2 bit 6
0359                 .equ   TCNT2_7 = 7 ; Timer/Counter 2 bit 7
0360                  
0361                 ; OCR2A - Timer/Counter2 Output Compare Register A
0362                 .equ   OCR2A_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
0363                 .equ   OCR2A_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
0364                 .equ   OCR2A_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
0365                 .equ   OCR2A_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
0366                 .equ   OCR2A_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
0367                 .equ   OCR2A_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
0368                 .equ   OCR2A_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
0369                 .equ   OCR2A_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
0370                  
0371                 ; OCR2B - Timer/Counter2 Output Compare Register B
0372                 .equ   OCR2B_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
0373                 .equ   OCR2B_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
0374                 .equ   OCR2B_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
0375                 .equ   OCR2B_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
0376                 .equ   OCR2B_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
0377                 .equ   OCR2B_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
0378                 .equ   OCR2B_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
0379                 .equ   OCR2B_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
0380                  
0381                 ; ASSR - Asynchronous Status Register
0382                 .equ   TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy
0383                 .equ   TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy
0384                 .equ   OCR2BUB = 2 ; Output Compare Register 2 Update Busy
0385                 .equ   OCR2AUB = 3 ; Output Compare Register2 Update Busy
0386                 .equ   TCN2UB  = 4 ; Timer/Counter2 Update Busy
0387                 .equ   AS2 = 5 ; Asynchronous Timer/Counter2
0388                 .equ   EXCLK   = 6 ; Enable External Clock Input
0389                  
0390                 ; GTCCR - General Timer Counter Control register
0391                 .equ   PSRASY  = 1 ; Prescaler Reset Timer/Counter2
0392                 .equ   PSR2    = PSRASY    ; For compatibility
0393                 ;.equ  TSM = 7 ; Timer/Counter Synchronization Mode
0394                  
0395                  
0396                 ; ***** AD_CONVERTER *****************
0397                 ; ADMUX - The ADC multiplexer Selection Register
0398                 .equ   MUX0    = 0 ; Analog Channel and Gain Selection Bits
0399                 .equ   MUX1    = 1 ; Analog Channel and Gain Selection Bits
0400                 .equ   MUX2    = 2 ; Analog Channel and Gain Selection Bits
0401                 .equ   MUX3    = 3 ; Analog Channel and Gain Selection Bits
0402                 .equ   ADLAR   = 5 ; Left Adjust Result
0403                 .equ   REFS0   = 6 ; Reference Selection Bit 0
0404                 .equ   REFS1   = 7 ; Reference Selection Bit 1
0405                  
0406                 ; ADCSRA - The ADC Control and Status register A
0407                 .equ   ADPS0   = 0 ; ADC  Prescaler Select Bits
0408                 .equ   ADPS1   = 1 ; ADC  Prescaler Select Bits
0409                 .equ   ADPS2   = 2 ; ADC  Prescaler Select Bits
0410                 .equ   ADIE    = 3 ; ADC Interrupt Enable
0411                 .equ   ADIF    = 4 ; ADC Interrupt Flag
0412                 .equ   ADATE   = 5 ; ADC  Auto Trigger Enable
0413                 .equ   ADSC    = 6 ; ADC Start Conversion
0414                 .equ   ADEN    = 7 ; ADC Enable
0415                  
0416                 ; ADCSRB - The ADC Control and Status register B
0417                 .equ   ADTS0   = 0 ; ADC Auto Trigger Source bit 0
0418                 .equ   ADTS1   = 1 ; ADC Auto Trigger Source bit 1
0419                 .equ   ADTS2   = 2 ; ADC Auto Trigger Source bit 2
0420                 .equ   ACME    = 6 ; 
0421                  
0422                 ; ADCH - ADC Data Register High Byte
0423                 .equ   ADCH0   = 0 ; ADC Data Register High Byte Bit 0
0424                 .equ   ADCH1   = 1 ; ADC Data Register High Byte Bit 1
0425                 .equ   ADCH2   = 2 ; ADC Data Register High Byte Bit 2
0426                 .equ   ADCH3   = 3 ; ADC Data Register High Byte Bit 3
0427                 .equ   ADCH4   = 4 ; ADC Data Register High Byte Bit 4
0428                 .equ   ADCH5   = 5 ; ADC Data Register High Byte Bit 5
0429                 .equ   ADCH6   = 6 ; ADC Data Register High Byte Bit 6
0430                 .equ   ADCH7   = 7 ; ADC Data Register High Byte Bit 7
0431                  
0432                 ; ADCL - ADC Data Register Low Byte
0433                 .equ   ADCL0   = 0 ; ADC Data Register Low Byte Bit 0
0434                 .equ   ADCL1   = 1 ; ADC Data Register Low Byte Bit 1
0435                 .equ   ADCL2   = 2 ; ADC Data Register Low Byte Bit 2
0436                 .equ   ADCL3   = 3 ; ADC Data Register Low Byte Bit 3
0437                 .equ   ADCL4   = 4 ; ADC Data Register Low Byte Bit 4
0438                 .equ   ADCL5   = 5 ; ADC Data Register Low Byte Bit 5
0439                 .equ   ADCL6   = 6 ; ADC Data Register Low Byte Bit 6
0440                 .equ   ADCL7   = 7 ; ADC Data Register Low Byte Bit 7
0441                  
0442                 ; DIDR0 - Digital Input Disable Register
0443                 .equ   ADC0D   = 0 ; 
0444                 .equ   ADC1D   = 1 ; 
0445                 .equ   ADC2D   = 2 ; 
0446                 .equ   ADC3D   = 3 ; 
0447                 .equ   ADC4D   = 4 ; 
0448                 .equ   ADC5D   = 5 ; 
0449                  
0450                  
0451                 ; ***** ANALOG_COMPARATOR ************
0452                 ; ACSR - Analog Comparator Control And Status Register
0453                 .equ   ACIS0   = 0 ; Analog Comparator Interrupt Mode Select bit 0
0454                 .equ   ACIS1   = 1 ; Analog Comparator Interrupt Mode Select bit 1
0455                 .equ   ACIC    = 2 ; Analog Comparator Input Capture Enable
0456                 .equ   ACIE    = 3 ; Analog Comparator Interrupt Enable
0457                 .equ   ACI = 4 ; Analog Comparator Interrupt Flag
0458                 .equ   ACO = 5 ; Analog Compare Output
0459                 .equ   ACBG    = 6 ; Analog Comparator Bandgap Select
0460                 .equ   ACD = 7 ; Analog Comparator Disable
0461                  
0462                 ; DIDR1 - Digital Input Disable Register 1
0463                 .equ   AIN0D   = 0 ; AIN0 Digital Input Disable
0464                 .equ   AIN1D   = 1 ; AIN1 Digital Input Disable
0465                  
0466                  
0467                 ; ***** PORTB ************************
0468                 ; PORTB - Port B Data Register
0469                 .equ   PORTB0  = 0 ; Port B Data Register bit 0
0470                 .equ   PB0 = 0 ; For compatibility
0471                 .equ   PORTB1  = 1 ; Port B Data Register bit 1
0472                 .equ   PB1 = 1 ; For compatibility
0473                 .equ   PORTB2  = 2 ; Port B Data Register bit 2
0474                 .equ   PB2 = 2 ; For compatibility
0475                 .equ   PORTB3  = 3 ; Port B Data Register bit 3
0476                 .equ   PB3 = 3 ; For compatibility
0477                 .equ   PORTB4  = 4 ; Port B Data Register bit 4
0478                 .equ   PB4 = 4 ; For compatibility
0479                 .equ   PORTB5  = 5 ; Port B Data Register bit 5
0480                 .equ   PB5 = 5 ; For compatibility
0481                 .equ   PORTB6  = 6 ; Port B Data Register bit 6
0482                 .equ   PB6 = 6 ; For compatibility
0483                 .equ   PORTB7  = 7 ; Port B Data Register bit 7
0484                 .equ   PB7 = 7 ; For compatibility
0485                  
0486                 ; DDRB - Port B Data Direction Register
0487                 .equ   DDB0    = 0 ; Port B Data Direction Register bit 0
0488                 .equ   DDB1    = 1 ; Port B Data Direction Register bit 1
0489                 .equ   DDB2    = 2 ; Port B Data Direction Register bit 2
0490                 .equ   DDB3    = 3 ; Port B Data Direction Register bit 3
0491                 .equ   DDB4    = 4 ; Port B Data Direction Register bit 4
0492                 .equ   DDB5    = 5 ; Port B Data Direction Register bit 5
0493                 .equ   DDB6    = 6 ; Port B Data Direction Register bit 6
0494                 .equ   DDB7    = 7 ; Port B Data Direction Register bit 7
0495                  
0496                 ; PINB - Port B Input Pins
0497                 .equ   PINB0   = 0 ; Port B Input Pins bit 0
0498                 .equ   PINB1   = 1 ; Port B Input Pins bit 1
0499                 .equ   PINB2   = 2 ; Port B Input Pins bit 2
0500                 .equ   PINB3   = 3 ; Port B Input Pins bit 3
0501                 .equ   PINB4   = 4 ; Port B Input Pins bit 4
0502                 .equ   PINB5   = 5 ; Port B Input Pins bit 5
0503                 .equ   PINB6   = 6 ; Port B Input Pins bit 6
0504                 .equ   PINB7   = 7 ; Port B Input Pins bit 7
0505                  
0506                  
0507                 ; ***** PORTC ************************
0508                 ; PORTC - Port C Data Register
0509                 .equ   PORTC0  = 0 ; Port C Data Register bit 0
0510                 .equ   PC0 = 0 ; For compatibility
0511                 .equ   PORTC1  = 1 ; Port C Data Register bit 1
0512                 .equ   PC1 = 1 ; For compatibility
0513                 .equ   PORTC2  = 2 ; Port C Data Register bit 2
0514                 .equ   PC2 = 2 ; For compatibility
0515                 .equ   PORTC3  = 3 ; Port C Data Register bit 3
0516                 .equ   PC3 = 3 ; For compatibility
0517                 .equ   PORTC4  = 4 ; Port C Data Register bit 4
0518                 .equ   PC4 = 4 ; For compatibility
0519                 .equ   PORTC5  = 5 ; Port C Data Register bit 5
0520                 .equ   PC5 = 5 ; For compatibility
0521                 .equ   PORTC6  = 6 ; Port C Data Register bit 6
0522                 .equ   PC6 = 6 ; For compatibility
0523                  
0524                 ; DDRC - Port C Data Direction Register
0525                 .equ   DDC0    = 0 ; Port C Data Direction Register bit 0
0526                 .equ   DDC1    = 1 ; Port C Data Direction Register bit 1
0527                 .equ   DDC2    = 2 ; Port C Data Direction Register bit 2
0528                 .equ   DDC3    = 3 ; Port C Data Direction Register bit 3
0529                 .equ   DDC4    = 4 ; Port C Data Direction Register bit 4
0530                 .equ   DDC5    = 5 ; Port C Data Direction Register bit 5
0531                 .equ   DDC6    = 6 ; Port C Data Direction Register bit 6
0532                  
0533                 ; PINC - Port C Input Pins
0534                 .equ   PINC0   = 0 ; Port C Input Pins bit 0
0535                 .equ   PINC1   = 1 ; Port C Input Pins bit 1
0536                 .equ   PINC2   = 2 ; Port C Input Pins bit 2
0537                 .equ   PINC3   = 3 ; Port C Input Pins bit 3
0538                 .equ   PINC4   = 4 ; Port C Input Pins bit 4
0539                 .equ   PINC5   = 5 ; Port C Input Pins bit 5
0540                 .equ   PINC6   = 6 ; Port C Input Pins bit 6
0541                  
0542                  
0543                 ; ***** PORTD ************************
0544                 ; PORTD - Port D Data Register
0545                 .equ   PORTD0  = 0 ; Port D Data Register bit 0
0546                 .equ   PD0 = 0 ; For compatibility
0547                 .equ   PORTD1  = 1 ; Port D Data Register bit 1
0548                 .equ   PD1 = 1 ; For compatibility
0549                 .equ   PORTD2  = 2 ; Port D Data Register bit 2
0550                 .equ   PD2 = 2 ; For compatibility
0551                 .equ   PORTD3  = 3 ; Port D Data Register bit 3
0552                 .equ   PD3 = 3 ; For compatibility
0553                 .equ   PORTD4  = 4 ; Port D Data Register bit 4
0554                 .equ   PD4 = 4 ; For compatibility
0555                 .equ   PORTD5  = 5 ; Port D Data Register bit 5
0556                 .equ   PD5 = 5 ; For compatibility
0557                 .equ   PORTD6  = 6 ; Port D Data Register bit 6
0558                 .equ   PD6 = 6 ; For compatibility
0559                 .equ   PORTD7  = 7 ; Port D Data Register bit 7
0560                 .equ   PD7 = 7 ; For compatibility
0561                  
0562                 ; DDRD - Port D Data Direction Register
0563                 .equ   DDD0    = 0 ; Port D Data Direction Register bit 0
0564                 .equ   DDD1    = 1 ; Port D Data Direction Register bit 1
0565                 .equ   DDD2    = 2 ; Port D Data Direction Register bit 2
0566                 .equ   DDD3    = 3 ; Port D Data Direction Register bit 3
0567                 .equ   DDD4    = 4 ; Port D Data Direction Register bit 4
0568                 .equ   DDD5    = 5 ; Port D Data Direction Register bit 5
0569                 .equ   DDD6    = 6 ; Port D Data Direction Register bit 6
0570                 .equ   DDD7    = 7 ; Port D Data Direction Register bit 7
0571                  
0572                 ; PIND - Port D Input Pins
0573                 .equ   PIND0   = 0 ; Port D Input Pins bit 0
0574                 .equ   PIND1   = 1 ; Port D Input Pins bit 1
0575                 .equ   PIND2   = 2 ; Port D Input Pins bit 2
0576                 .equ   PIND3   = 3 ; Port D Input Pins bit 3
0577                 .equ   PIND4   = 4 ; Port D Input Pins bit 4
0578                 .equ   PIND5   = 5 ; Port D Input Pins bit 5
0579                 .equ   PIND6   = 6 ; Port D Input Pins bit 6
0580                 .equ   PIND7   = 7 ; Port D Input Pins bit 7
0581                  
0582                  
0583                 ; ***** TIMER_COUNTER_0 **************
0584                 ; TIMSK0 - Timer/Counter0 Interrupt Mask Register
0585                 .equ   TOIE0   = 0 ; Timer/Counter0 Overflow Interrupt Enable
0586                 .equ   OCIE0A  = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
0587                 .equ   OCIE0B  = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
0588                  
0589                 ; TIFR0 - Timer/Counter0 Interrupt Flag register
0590                 .equ   TOV0    = 0 ; Timer/Counter0 Overflow Flag
0591                 .equ   OCF0A   = 1 ; Timer/Counter0 Output Compare Flag 0A
0592                 .equ   OCF0B   = 2 ; Timer/Counter0 Output Compare Flag 0B
0593                  
0594                 ; TCCR0A - Timer/Counter  Control Register A
0595                 .equ   WGM00   = 0 ; Waveform Generation Mode
0596                 .equ   WGM01   = 1 ; Waveform Generation Mode
0597                 .equ   COM0B0  = 4 ; Compare Output Mode, Fast PWm
0598                 .equ   COM0B1  = 5 ; Compare Output Mode, Fast PWm
0599                 .equ   COM0A0  = 6 ; Compare Output Mode, Phase Correct PWM Mode
0600                 .equ   COM0A1  = 7 ; Compare Output Mode, Phase Correct PWM Mode
0601                  
0602                 ; TCCR0B - Timer/Counter Control Register B
0603                 .equ   CS00    = 0 ; Clock Select
0604                 .equ   CS01    = 1 ; Clock Select
0605                 .equ   CS02    = 2 ; Clock Select
0606                 .equ   WGM02   = 3 ; 
0607                 .equ   FOC0B   = 6 ; Force Output Compare B
0608                 .equ   FOC0A   = 7 ; Force Output Compare A
0609                  
0610                 ; TCNT0 - Timer/Counter0
0611                 .equ   TCNT0_0 = 0 ; 
0612                 .equ   TCNT0_1 = 1 ; 
0613                 .equ   TCNT0_2 = 2 ; 
0614                 .equ   TCNT0_3 = 3 ; 
0615                 .equ   TCNT0_4 = 4 ; 
0616                 .equ   TCNT0_5 = 5 ; 
0617                 .equ   TCNT0_6 = 6 ; 
0618                 .equ   TCNT0_7 = 7 ; 
0619                  
0620                 ; OCR0A - Timer/Counter0 Output Compare Register
0621                 .equ   OCR0A_0 = 0 ; 
0622                 .equ   OCR0A_1 = 1 ; 
0623                 .equ   OCR0A_2 = 2 ; 
0624                 .equ   OCR0A_3 = 3 ; 
0625                 .equ   OCR0A_4 = 4 ; 
0626                 .equ   OCR0A_5 = 5 ; 
0627                 .equ   OCR0A_6 = 6 ; 
0628                 .equ   OCR0A_7 = 7 ; 
0629                  
0630                 ; OCR0B - Timer/Counter0 Output Compare Register
0631                 .equ   OCR0B_0 = 0 ; 
0632                 .equ   OCR0B_1 = 1 ; 
0633                 .equ   OCR0B_2 = 2 ; 
0634                 .equ   OCR0B_3 = 3 ; 
0635                 .equ   OCR0B_4 = 4 ; 
0636                 .equ   OCR0B_5 = 5 ; 
0637                 .equ   OCR0B_6 = 6 ; 
0638                 .equ   OCR0B_7 = 7 ; 
0639                  
0640                 ; GTCCR - General Timer/Counter Control Register
0641                 ;.equ  PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
0642                 .equ   PSR10   = PSRSYNC   ; For compatibility
0643                 ;.equ  TSM = 7 ; Timer/Counter Synchronization Mode
0644                  
0645                  
0646                 ; ***** EXTERNAL_INTERRUPT ***********
0647                 ; EICRA - External Interrupt Control Register
0648                 .equ   ISC00   = 0 ; External Interrupt Sense Control 0 Bit 0
0649                 .equ   ISC01   = 1 ; External Interrupt Sense Control 0 Bit 1
0650                 .equ   ISC10   = 2 ; External Interrupt Sense Control 1 Bit 0
0651                 .equ   ISC11   = 3 ; External Interrupt Sense Control 1 Bit 1
0652                  
0653                 ; EIMSK - External Interrupt Mask Register
0654                 .equ   INT0    = 0 ; External Interrupt Request 0 Enable
0655                 .equ   INT1    = 1 ; External Interrupt Request 1 Enable
0656                  
0657                 ; EIFR - External Interrupt Flag Register
0658                 .equ   INTF0   = 0 ; External Interrupt Flag 0
0659                 .equ   INTF1   = 1 ; External Interrupt Flag 1
0660                  
0661                 ; PCICR - Pin Change Interrupt Control Register
0662                 .equ   PCIE0   = 0 ; Pin Change Interrupt Enable 0
0663                 .equ   PCIE1   = 1 ; Pin Change Interrupt Enable 1
0664                 .equ   PCIE2   = 2 ; Pin Change Interrupt Enable 2
0665                  
0666                 ; PCMSK2 - Pin Change Mask Register 2
0667                 .equ   PCINT16 = 0 ; Pin Change Enable Mask 16
0668                 .equ   PCINT17 = 1 ; Pin Change Enable Mask 17
0669                 .equ   PCINT18 = 2 ; Pin Change Enable Mask 18
0670                 .equ   PCINT19 = 3 ; Pin Change Enable Mask 19
0671                 .equ   PCINT20 = 4 ; Pin Change Enable Mask 20
0672                 .equ   PCINT21 = 5 ; Pin Change Enable Mask 21
0673                 .equ   PCINT22 = 6 ; Pin Change Enable Mask 22
0674                 .equ   PCINT23 = 7 ; Pin Change Enable Mask 23
0675                  
0676                 ; PCMSK1 - Pin Change Mask Register 1
0677                 .equ   PCINT8  = 0 ; Pin Change Enable Mask 8
0678                 .equ   PCINT9  = 1 ; Pin Change Enable Mask 9
0679                 .equ   PCINT10 = 2 ; Pin Change Enable Mask 10
0680                 .equ   PCINT11 = 3 ; Pin Change Enable Mask 11
0681                 .equ   PCINT12 = 4 ; Pin Change Enable Mask 12
0682                 .equ   PCINT13 = 5 ; Pin Change Enable Mask 13
0683                 .equ   PCINT14 = 6 ; Pin Change Enable Mask 14
0684                  
0685                 ; PCMSK0 - Pin Change Mask Register 0
0686                 .equ   PCINT0  = 0 ; Pin Change Enable Mask 0
0687                 .equ   PCINT1  = 1 ; Pin Change Enable Mask 1
0688                 .equ   PCINT2  = 2 ; Pin Change Enable Mask 2
0689                 .equ   PCINT3  = 3 ; Pin Change Enable Mask 3
0690                 .equ   PCINT4  = 4 ; Pin Change Enable Mask 4
0691                 .equ   PCINT5  = 5 ; Pin Change Enable Mask 5
0692                 .equ   PCINT6  = 6 ; Pin Change Enable Mask 6
0693                 .equ   PCINT7  = 7 ; Pin Change Enable Mask 7
0694                  
0695                 ; PCIFR - Pin Change Interrupt Flag Register
0696                 .equ   PCIF0   = 0 ; Pin Change Interrupt Flag 0
0697                 .equ   PCIF1   = 1 ; Pin Change Interrupt Flag 1
0698                 .equ   PCIF2   = 2 ; Pin Change Interrupt Flag 2
0699                  
0700                  
0701                 ; ***** SPI **************************
0702                 ; SPDR - SPI Data Register
0703                 .equ   SPDR0   = 0 ; SPI Data Register bit 0
0704                 .equ   SPDR1   = 1 ; SPI Data Register bit 1
0705                 .equ   SPDR2   = 2 ; SPI Data Register bit 2
0706                 .equ   SPDR3   = 3 ; SPI Data Register bit 3
0707                 .equ   SPDR4   = 4 ; SPI Data Register bit 4
0708                 .equ   SPDR5   = 5 ; SPI Data Register bit 5
0709                 .equ   SPDR6   = 6 ; SPI Data Register bit 6
0710                 .equ   SPDR7   = 7 ; SPI Data Register bit 7
0711                  
0712                 ; SPSR - SPI Status Register
0713                 .equ   SPI2X   = 0 ; Double SPI Speed Bit
0714                 .equ   WCOL    = 6 ; Write Collision Flag
0715                 .equ   SPIF    = 7 ; SPI Interrupt Flag
0716                  
0717                 ; SPCR - SPI Control Register
0718                 .equ   SPR0    = 0 ; SPI Clock Rate Select 0
0719                 .equ   SPR1    = 1 ; SPI Clock Rate Select 1
0720                 .equ   CPHA    = 2 ; Clock Phase
0721                 .equ   CPOL    = 3 ; Clock polarity
0722                 .equ   MSTR    = 4 ; Master/Slave Select
0723                 .equ   DORD    = 5 ; Data Order
0724                 .equ   SPE = 6 ; SPI Enable
0725                 .equ   SPIE    = 7 ; SPI Interrupt Enable
0726                  
0727                  
0728                 ; ***** WATCHDOG *********************
0729                 ; WDTCSR - Watchdog Timer Control Register
0730                 .equ   WDP0    = 0 ; Watch Dog Timer Prescaler bit 0
0731                 .equ   WDP1    = 1 ; Watch Dog Timer Prescaler bit 1
0732                 .equ   WDP2    = 2 ; Watch Dog Timer Prescaler bit 2
0733                 .equ   WDE = 3 ; Watch Dog Enable
0734                 .equ   WDCE    = 4 ; Watchdog Change Enable
0735                 .equ   WDP3    = 5 ; Watchdog Timer Prescaler Bit 3
0736                 .equ   WDIE    = 6 ; Watchdog Timeout Interrupt Enable
0737                 .equ   WDIF    = 7 ; Watchdog Timeout Interrupt Flag
0738                  
0739                  
0740                 ; ***** CPU **************************
0741                 ; SREG - Status Register
0742                 .equ   SREG_C  = 0 ; Carry Flag
0743                 .equ   SREG_Z  = 1 ; Zero Flag
0744                 .equ   SREG_N  = 2 ; Negative Flag
0745                 .equ   SREG_V  = 3 ; Two's Complement Overflow Flag
0746                 .equ   SREG_S  = 4 ; Sign Bit
0747                 .equ   SREG_H  = 5 ; Half Carry Flag
0748                 .equ   SREG_T  = 6 ; Bit Copy Storage
0749                 .equ   SREG_I  = 7 ; Global Interrupt Enable
0750                  
0751                 ; OSCCAL - Oscillator Calibration Value
0752                 .equ   CAL0    = 0 ; Oscillator Calibration Value Bit0
0753                 .equ   CAL1    = 1 ; Oscillator Calibration Value Bit1
0754                 .equ   CAL2    = 2 ; Oscillator Calibration Value Bit2
0755                 .equ   CAL3    = 3 ; Oscillator Calibration Value Bit3
0756                 .equ   CAL4    = 4 ; Oscillator Calibration Value Bit4
0757                 .equ   CAL5    = 5 ; Oscillator Calibration Value Bit5
0758                 .equ   CAL6    = 6 ; Oscillator Calibration Value Bit6
0759                 .equ   CAL7    = 7 ; Oscillator Calibration Value Bit7
0760                  
0761                 ; CLKPR - Clock Prescale Register
0762                 .equ   CLKPS0  = 0 ; Clock Prescaler Select Bit 0
0763                 .equ   CLKPS1  = 1 ; Clock Prescaler Select Bit 1
0764                 .equ   CLKPS2  = 2 ; Clock Prescaler Select Bit 2
0765                 .equ   CLKPS3  = 3 ; Clock Prescaler Select Bit 3
0766                 .equ   CLKPCE  = 7 ; Clock Prescaler Change Enable
0767                  
0768                 ; SPMCSR - Store Program Memory Control and Status Register
0769                 .equ   SELFPRGEN   = 0 ; Self Programming Enable
0770                 .equ   PGERS   = 1 ; Page Erase
0771                 .equ   PGWRT   = 2 ; Page Write
0772                 .equ   BLBSET  = 3 ; Boot Lock Bit Set
0773                 .equ   RWWSRE  = 4 ; Read-While-Write section read enable
0774                 .equ   RWWSB   = 6 ; Read-While-Write Section Busy
0775                 .equ   SPMIE   = 7 ; SPM Interrupt Enable
0776                  
0777                 ; MCUCR - MCU Control Register
0778                 .equ   IVCE    = 0 ; 
0779                 .equ   IVSEL   = 1 ; 
0780                 .equ   PUD = 4 ; 
0781                 .equ   BODSE   = 5 ; BOD Sleep Enable
0782                 .equ   BODS    = 6 ; BOD Sleep
0783                  
0784                 ; MCUSR - MCU Status Register
0785                 .equ   PORF    = 0 ; Power-on reset flag
0786                 .equ   EXTRF   = 1 ; External Reset Flag
0787                 .equ   EXTREF  = EXTRF ; For compatibility
0788                 .equ   BORF    = 2 ; Brown-out Reset Flag
0789                 .equ   WDRF    = 3 ; Watchdog Reset Flag
0790                  
0791                 ; SMCR - Sleep Mode Control Register
0792                 .equ   SE  = 0 ; Sleep Enable
0793                 .equ   SM0 = 1 ; Sleep Mode Select Bit 0
0794                 .equ   SM1 = 2 ; Sleep Mode Select Bit 1
0795                 .equ   SM2 = 3 ; Sleep Mode Select Bit 2
0796                  
0797                 ; GPIOR2 - General Purpose I/O Register 2
0798                 .equ   GPIOR20 = 0 ; 
0799                 .equ   GPIOR21 = 1 ; 
0800                 .equ   GPIOR22 = 2 ; 
0801                 .equ   GPIOR23 = 3 ; 
0802                 .equ   GPIOR24 = 4 ; 
0803                 .equ   GPIOR25 = 5 ; 
0804                 .equ   GPIOR26 = 6 ; 
0805                 .equ   GPIOR27 = 7 ; 
0806                  
0807                 ; GPIOR1 - General Purpose I/O Register 1
0808                 .equ   GPIOR10 = 0 ; 
0809                 .equ   GPIOR11 = 1 ; 
0810                 .equ   GPIOR12 = 2 ; 
0811                 .equ   GPIOR13 = 3 ; 
0812                 .equ   GPIOR14 = 4 ; 
0813                 .equ   GPIOR15 = 5 ; 
0814                 .equ   GPIOR16 = 6 ; 
0815                 .equ   GPIOR17 = 7 ; 
0816                  
0817                 ; GPIOR0 - General Purpose I/O Register 0
0818                 .equ   GPIOR00 = 0 ; 
0819                 .equ   GPIOR01 = 1 ; 
0820                 .equ   GPIOR02 = 2 ; 
0821                 .equ   GPIOR03 = 3 ; 
0822                 .equ   GPIOR04 = 4 ; 
0823                 .equ   GPIOR05 = 5 ; 
0824                 .equ   GPIOR06 = 6 ; 
0825                 .equ   GPIOR07 = 7 ; 
0826                  
0827                 ; PRR - Power Reduction Register
0828                 .equ   PRADC   = 0 ; Power Reduction ADC
0829                 .equ   PRUSART0    = 1 ; Power Reduction USART
0830                 .equ   PRSPI   = 2 ; Power Reduction Serial Peripheral Interface
0831                 .equ   PRTIM1  = 3 ; Power Reduction Timer/Counter1
0832                 .equ   PRTIM0  = 5 ; Power Reduction Timer/Counter0
0833                 .equ   PRTIM2  = 6 ; Power Reduction Timer/Counter2
0834                 .equ   PRTWI   = 7 ; Power Reduction TWI
0835                  
0836                  
0837                 ; ***** EEPROM ***********************
0838                 ; EEARL - EEPROM Address Register Low Byte
0839                 .equ   EEAR0   = 0 ; EEPROM Read/Write Access Bit 0
0840                 .equ   EEAR1   = 1 ; EEPROM Read/Write Access Bit 1
0841                 .equ   EEAR2   = 2 ; EEPROM Read/Write Access Bit 2
0842                 .equ   EEAR3   = 3 ; EEPROM Read/Write Access Bit 3
0843                 .equ   EEAR4   = 4 ; EEPROM Read/Write Access Bit 4
0844                 .equ   EEAR5   = 5 ; EEPROM Read/Write Access Bit 5
0845                 .equ   EEAR6   = 6 ; EEPROM Read/Write Access Bit 6
0846                 .equ   EEAR7   = 7 ; EEPROM Read/Write Access Bit 7
0847                  
0848                 ; EEARH - EEPROM Address Register High Byte
0849                 .equ   EEAR8   = 0 ; EEPROM Read/Write Access Bit 8
0850                 .equ   EEAR9   = 1 ; EEPROM Read/Write Access Bit 9
0851                  
0852                 ; EEDR - EEPROM Data Register
0853                 .equ   EEDR0   = 0 ; EEPROM Data Register bit 0
0854                 .equ   EEDR1   = 1 ; EEPROM Data Register bit 1
0855                 .equ   EEDR2   = 2 ; EEPROM Data Register bit 2
0856                 .equ   EEDR3   = 3 ; EEPROM Data Register bit 3
0857                 .equ   EEDR4   = 4 ; EEPROM Data Register bit 4
0858                 .equ   EEDR5   = 5 ; EEPROM Data Register bit 5
0859                 .equ   EEDR6   = 6 ; EEPROM Data Register bit 6
0860                 .equ   EEDR7   = 7 ; EEPROM Data Register bit 7
0861                  
0862                 ; EECR - EEPROM Control Register
0863                 .equ   EERE    = 0 ; EEPROM Read Enable
0864                 .equ   EEPE    = 1 ; EEPROM Write Enable
0865                 .equ   EEMPE   = 2 ; EEPROM Master Write Enable
0866                 .equ   EERIE   = 3 ; EEPROM Ready Interrupt Enable
0867                 .equ   EEPM0   = 4 ; EEPROM Programming Mode Bit 0
0868                 .equ   EEPM1   = 5 ; EEPROM Programming Mode Bit 1
0869                  
0870                  
0871                  
0872                 ; ***** LOCKSBITS ********************************************************
0873                 .equ   LB1 = 0 ; Lock bit
0874                 .equ   LB2 = 1 ; Lock bit
0875                 .equ   BLB01   = 2 ; Boot Lock bit
0876                 .equ   BLB02   = 3 ; Boot Lock bit
0877                 .equ   BLB11   = 4 ; Boot lock bit
0878                 .equ   BLB12   = 5 ; Boot lock bit
0879                  
0880                  
0881                 ; ***** FUSES ************************************************************
0882                 ; LOW fuse bits
0883                 .equ   CKSEL0  = 0 ; Select Clock Source
0884                 .equ   CKSEL1  = 1 ; Select Clock Source
0885                 .equ   CKSEL2  = 2 ; Select Clock Source
0886                 .equ   CKSEL3  = 3 ; Select Clock Source
0887                 .equ   SUT0    = 4 ; Select start-up time
0888                 .equ   SUT1    = 5 ; Select start-up time
0889                 .equ   CKOUT   = 6 ; Clock output
0890                 .equ   CKDIV8  = 7 ; Divide clock by 8
0891                  
0892                 ; HIGH fuse bits
0893                 .equ   BOOTRST = 0 ; Select reset vector
0894                 .equ   BOOTSZ0 = 1 ; Select boot size
0895                 .equ   BOOTSZ1 = 2 ; Select boot size
0896                 .equ   EESAVE  = 3 ; EEPROM memory is preserved through chip erase
0897                 .equ   WDTON   = 4 ; Watchdog Timer Always On
0898                 .equ   SPIEN   = 5 ; Enable Serial programming and Data Downloading
0899                 .equ   DWEN    = 6 ; debugWIRE Enable
0900                 .equ   RSTDISBL    = 7 ; External reset disable
0901                  
0902                 ; EXTENDED fuse bits
0903                 .equ   BODLEVEL0   = 0 ; Brown-out Detector trigger level
0904                 .equ   BODLEVEL1   = 1 ; Brown-out Detector trigger level
0905                 .equ   BODLEVEL2   = 2 ; Brown-out Detector trigger level
0906                  
0907                  
0908                  
0909                 ; ***** CPU REGISTER DEFINITIONS *****************************************
0910                 .def   XH  = r27
0911                 .def   XL  = r26
0912                 .def   YH  = r29
0913                 .def   YL  = r28
0914                 .def   ZH  = r31
0915                 .def   ZL  = r30
0916                  
0917                  
0918                  
0919                 ; ***** DATA MEMORY DECLARATIONS *****************************************
0920                 .equ   FLASHEND    = 0x3fff    ; Note: Word address
0921                 .equ   IOEND   = 0x00ff
0922                 .equ   SRAM_START  = 0x0100
0923                 .equ   SRAM_SIZE   = 2048
0924                 .equ   RAMEND  = 0x08ff
0925                 .equ   XRAMEND = 0x0000
0926                 .equ   E2END   = 0x03ff
0927                 .equ   EEPROMEND   = 0x03ff
0928                 .equ   EEADRBITS   = 10
0929                 #pragma AVRPART MEMORY PROG_FLASH 32768
0930                 #pragma AVRPART MEMORY EEPROM 1024
0931                 #pragma AVRPART MEMORY INT_SRAM SIZE 2048
0932                 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
0933                  
0934                  
0935                  
0936                 ; ***** BOOTLOADER DECLARATIONS ******************************************
0937                 .equ   NRWW_START_ADDR = 0x3800
0938                 .equ   NRWW_STOP_ADDR  = 0x3fff
0939                 .equ   RWW_START_ADDR  = 0x0
0940                 .equ   RWW_STOP_ADDR   = 0x37ff
0941                 .equ   PAGESIZE    = 64
0942                 .equ   FIRSTBOOTSTART  = 0x3f00
0943                 .equ   SECONDBOOTSTART = 0x3e00
0944                 .equ   THIRDBOOTSTART  = 0x3c00
0945                 .equ   FOURTHBOOTSTART = 0x3800
0946                 .equ   SMALLBOOTSTART  = FIRSTBOOTSTART
0947                 .equ   LARGEBOOTSTART  = FOURTHBOOTSTART
0948                  
0949                  
0950                  
0951                 ; ***** INTERRUPT VECTORS ************************************************
0952                 .equ   INT0addr    = 0x0002    ; External Interrupt Request 0
0953                 .equ   INT1addr    = 0x0004    ; External Interrupt Request 1
0954                 .equ   PCI0addr    = 0x0006    ; Pin Change Interrupt Request 0
0955                 .equ   PCI1addr    = 0x0008    ; Pin Change Interrupt Request 0
0956                 .equ   PCI2addr    = 0x000a    ; Pin Change Interrupt Request 1
0957                 .equ   WDTaddr = 0x000c    ; Watchdog Time-out Interrupt
0958                 .equ   OC2Aaddr    = 0x000e    ; Timer/Counter2 Compare Match A
0959                 .equ   OC2Baddr    = 0x0010    ; Timer/Counter2 Compare Match A
0960                 .equ   OVF2addr    = 0x0012    ; Timer/Counter2 Overflow
0961                 .equ   ICP1addr    = 0x0014    ; Timer/Counter1 Capture Event
0962                 .equ   OC1Aaddr    = 0x0016    ; Timer/Counter1 Compare Match A
0963                 .equ   OC1Baddr    = 0x0018    ; Timer/Counter1 Compare Match B
0964                 .equ   OVF1addr    = 0x001a    ; Timer/Counter1 Overflow
0965                 .equ   OC0Aaddr    = 0x001c    ; TimerCounter0 Compare Match A
0966                 .equ   OC0Baddr    = 0x001e    ; TimerCounter0 Compare Match B
0967                 .equ   OVF0addr    = 0x0020    ; Timer/Couner0 Overflow
0968                 .equ   SPIaddr = 0x0022    ; SPI Serial Transfer Complete
0969                 .equ   URXCaddr    = 0x0024    ; USART Rx Complete
0970                 .equ   UDREaddr    = 0x0026    ; USART, Data Register Empty
0971                 .equ   UTXCaddr    = 0x0028    ; USART Tx Complete
0972                 .equ   ADCCaddr    = 0x002a    ; ADC Conversion Complete
0973                 .equ   ERDYaddr    = 0x002c    ; EEPROM Ready
0974                 .equ   ACIaddr = 0x002e    ; Analog Comparator
0975                 .equ   TWIaddr = 0x0030    ; Two-wire Serial Interface
0976                 .equ   SPMRaddr    = 0x0032    ; Store Program Memory Read
0977                  
0978                 .equ   INT_VECTORS_SIZE    = 52    ; size in words
0979                  
0980                 #endif  /* _M328PDEF_INC_ */
0981                  
0982                 ; ***** END OF FILE ******************************************************
0983                  
0984                 .equ       SCLPIN=PORTC5
0985                 .equ       SDAPORT=PORTC
0986                 .equ       SDAPIN=PORTC4
0987                  
0988                 .CSEG
0989                  
0990                 .ORG       $0
0991000000 c078         RJMP    Start
0992                  
0993                 .ORG       INT_VECTORS_SIZE
0994                 ;------------------------------
0995                 i2c_init:
0996000034 983d         CBI SCLPORT-1,SCLPIN
0997000035 983c         CBI SDAPORT-1,SDAPIN
0998000036 9844         CBI SDAPORT,SDAPIN
0999000037 9845         CBI SCLPORT,SCLPIN
1000000038 9508         RET
1001                  
1002                 ;------------------------------
1003                 i2c_start:
1004000039 9a3c         SBI SDAPORT-1,SDAPIN
100500003a 9508         RET
1006                  
1007                 ;------------------------------
1008                 i2c_restart:
100900003b 983d         CBI SCLPORT-1,SCLPIN
101000003c 983d         CBI SCLPORT-1,SCLPIN
101100003d 9a3c         SBI SDAPORT-1,SDAPIN
101200003e 9508         RET
1013                  
1014                 ;------------------------------
1015                 i2c_write:
101600003f e098         LDI R25,8
1017                 i2c_write_loop:
1018000040 9a3d         SBI SCLPORT-1,SCLPIN
1019000041 fd87         SBRC    R24,7
1020000042 983c         CBI SDAPORT-1,SDAPIN
1021000043 ff87         SBRS    R24,7
1022000044 9a3c         SBI SDAPORT-1,SDAPIN
1023000045 1f88         ROL R24
1024000046 983d         CBI SCLPORT-1,SCLPIN
1025                 i2c_write_loop1:
1026000047 9b35         SBIS    SCLPORT-2,SCLPIN
1027000048 cffe         RJMP    i2c_write_loop1
1028000049 0000         NOP
102900004a 959a         DEC R25
103000004b f7a1         BRNE    i2c_write_loop
103100004c 0000         NOP
103200004d 9a3d         SBI SCLPORT-1,SCLPIN
103300004e 983c         CBI SDAPORT-1,SDAPIN
103400004f 983c         CBI SDAPORT-1,SDAPIN
1035000050 983c         CBI SDAPORT-1,SDAPIN
1036000051 983d         CBI SCLPORT-1,SCLPIN
1037000052 2788         CLR R24
1038000053 9b34         SBIS    SDAPORT-2,SDAPIN
1039000054 9583         INC R24
1040000055 983d         CBI SCLPORT-1,SCLPIN
1041000056 0000         NOP
1042000057 9a3d         SBI SCLPORT-1,SCLPIN
1043000058 9508         RET
1044                  
1045                 ;------------------------------
1046                 i2c_read:
1047000059 e098         LDI R25,8
104800005a fb80         BST R24,0
1049                 i2c_read_loop:
105000005b 9a3d         SBI SCLPORT-1,SCLPIN
105100005c 9a3d         SBI SCLPORT-1,SCLPIN
105200005d 9a3d         SBI SCLPORT-1,SCLPIN
105300005e f980         BLD R24,0
105400005f 0f88         LSL R24
1055000060 983d         CBI SCLPORT-1,SCLPIN
1056000061 9468         SET
1057000062 9b34         SBIS    SDAPORT-2,SDAPIN
1058000063 94e8         CLT
1059000064 959a         DEC R25
1060000065 f7a9         BRNE    i2c_read_loop
1061000066 f980         BLD R24,0
1062000067 9a3d         SBI SCLPORT-1,SCLPIN
1063000068 1f99         ROL R25
1064000069 ff90         SBRS    R25,0
106500006a 9a3c         SBI SDAPORT-1,SDAPIN
106600006b fd90         SBRC    R25,0
106700006c 983c         CBI SDAPORT-1,SDAPIN
106800006d 983d         CBI SCLPORT-1,SCLPIN
106900006e 983d         CBI SCLPORT-1,SCLPIN
107000006f 983d         CBI SCLPORT-1,SCLPIN
1071000070 983d         CBI SCLPORT-1,SCLPIN
1072000071 9a3d         SBI SCLPORT-1,SCLPIN
1073000072 983c         CBI SDAPORT-1,SDAPIN
1074000073 9508         RET
1075                  
1076                 ;------------------------------
1077                 i2c_stop:
1078000074 9a3c         SBI SDAPORT-1,SDAPIN
1079000075 983d         CBI SCLPORT-1,SCLPIN
1080000076 983d         CBI SCLPORT-1,SCLPIN
1081000077 983c         CBI SDAPORT-1,SDAPIN
1082000078 9508         RET
1083                  
1084                 ;------------------------------
1085                 Start:
1086000079 ef0f         LDI R16,Low(RAMEND)
108700007a bf0d         OUT SPL,R16
108800007b e008         LDI R16,High(RAMEND)
108900007c bf0e         OUT SPH,R16
109000007d 940e 0034    CALL    i2c_init
1091                 Loop:
109200007f 940e 0039    CALL    i2c_start
1093000081 ec80         LDI R24,$C0
1094000082 940e 003f    CALL    i2c_write
1095000084 e087         LDI R24,$07
1096000085 940e 003f    CALL    i2c_write
1097000087 ef8f         LDI R24,$FF
1098000088 940e 003f    CALL    i2c_write
109900008a 940e 0074    CALL    i2c_stop
110000008c 940e 0039    CALL    i2c_start
110100008e e880         LDI R24,$80
110200008f 940e 003f    CALL    i2c_write
1103000091 e083         LDI R24,$03
1104000092 940e 003f    CALL    i2c_write
1105000094 e181         LDI R24,$11
1106000095 940e 003f    CALL    i2c_write
1107000097 940e 0074    CALL    i2c_stop
1108                 Loop1:
1109000099 940e 0039    CALL    i2c_start
111000009b e880         LDI R24,$80
111100009c 940e 003f    CALL    i2c_write
111200009e e080         LDI R24,$00
111300009f 940e 003f    CALL    i2c_write
11140000a1 940e 003b    CALL    i2c_restart
11150000a3 e881         LDI R24,$81
11160000a4 940e 003f    CALL    i2c_write
11170000a6 e081         LDI R24,$01
11180000a7 940e 0059    CALL    i2c_read
11190000a9 940e 0074    CALL    i2c_stop
11200000ab 7081         ANDI    R24,$01
11210000ac f761         BRNE    Loop1
11220000ad 940e 0039    CALL    i2c_start
11230000af e880         LDI R24,$80
11240000b0 940e 003f    CALL    i2c_write
11250000b2 e081         LDI R24,$01
11260000b3 940e 003f    CALL    i2c_write
11270000b5 940e 003b    CALL    i2c_restart
11280000b7 e881         LDI R24,$81
11290000b8 940e 003f    CALL    i2c_write
11300000ba e080         LDI R24,$00
11310000bb 940e 0059    CALL    i2c_read
11320000bd e081         LDI R24,$01
11330000be 940e 0059    CALL    i2c_read
11340000c0 940e 0074    CALL    i2c_stop
11350000c2 cfbc         RJMP    Loop
1136 
1137 
1138RESOURCE USE INFORMATION
1139------------------------
1140 
1141Notice:
1142The register and instruction counts are symbol table hit counts,
1143and hence implicitly used resources are not counted, eg, the
1144'lpm' instruction without operands implicitly uses r0 and z,
1145none of which are counted.
1146 
1147x,y,z are separate entities in the symbol table and are
1148counted separately from r26..r31 here.
1149 
1150.dseg memory usage only counts static data declared with .byte
1151 
1152ATmega328P register use summary:
1153r0 :   0 r1 :   0 r2 :   0 r3 :   0 r4 :   0 r5 :   0 r6 :   0 r7 :   0 
1154r8 :   0 r9 :   0 r10:   0 r11:   0 r12:   0 r13:   0 r14:   0 r15:   0 
1155r16:   4 r17:   0 r18:   0 r19:   0 r20:   0 r21:   0 r22:   0 r23:   0 
1156r24:  25 r25:   7 r26:   0 r27:   0 r28:   0 r29:   0 r30:   0 r31:   0 
1157x  :   0 y  :   0 z  :   0 
1158Registers used: 3 out of 35 (8.6%)
1159 
1160ATmega328P instruction use summary:
1161.lds  :   0 .sts  :   0 adc   :   0 add   :   0 adiw  :   0 and   :   0 
1162andi  :   1 asr   :   0 bclr  :   0 bld   :   2 brbc  :   0 brbs  :   0 
1163brcc  :   0 brcs  :   0 break :   0 breq  :   0 brge  :   0 brhc  :   0 
1164brhs  :   0 brid  :   0 brie  :   0 brlo  :   0 brlt  :   0 brmi  :   0 
1165brne  :   3 brpl  :   0 brsh  :   0 brtc  :   0 brts  :   0 brvc  :   0 
1166brvs  :   0 bset  :   0 bst   :   1 call  :  26 cbi   :  23 cbr   :   0 
1167clc   :   0 clh   :   0 cli   :   0 cln   :   0 clr   :   1 cls   :   0 
1168clt   :   1 clv   :   0 clz   :   0 com   :   0 cp    :   0 cpc   :   0 
1169cpi   :   0 cpse  :   0 dec   :   2 eor   :   0 fmul  :   0 fmuls :   0 
1170fmulsu:   0 icall :   0 ijmp  :   0 in    :   0 inc   :   1 jmp   :   0 
1171ld    :   0 ldd   :   0 ldi   :  19 lds   :   0 lpm   :   0 lsl   :   1 
1172lsr   :   0 mov   :   0 movw  :   0 mul   :   0 muls  :   0 mulsu :   0 
1173neg   :   0 nop   :   3 or    :   0 ori   :   0 out   :   2 pop   :   0 
1174push  :   0 rcall :   0 ret   :   6 reti  :   0 rjmp  :   3 rol   :   2 
1175ror   :   0 sbc   :   0 sbci  :   0 sbi   :  13 sbic  :   0 sbis  :   3 
1176sbiw  :   0 sbr   :   0 sbrc  :   2 sbrs  :   2 sec   :   0 seh   :   0 
1177sei   :   0 sen   :   0 ser   :   0 ses   :   0 set   :   1 sev   :   0 
1178sez   :   0 sleep :   0 spm   :   0 st    :   0 std   :   0 sts   :   0 
1179sub   :   0 subi  :   0 swap  :   0 tst   :   0 wdr   :   0 
1180Instructions used: 22 out of 113 (19.5%)
1181 
1182ATmega328P memory use summary [bytes]:
1183Segment   Begin    End      Code   Data   Used    Size   Use%
1184---------------------------------------------------------------
1185[.cseg] 0x000000 0x000186    288      0    288   32768   0.9%
1186[.dseg] 0x000100 0x000100      0      0      0    2048   0.0%
1187[.eseg] 0x000000 0x000000      0      0      0    1024   0.0%
1188 
1189Assembly complete, 0 errors, 0 warnings

Пт, 04/12/2020 - 21:28

#20

Komandir

Offline

Зарегистрирован: 18.08.2018

Это просто константы. Они прописаны в ...inc и заменяются реальными номерами портов и константами пинов для портов ...

Пт, 04/12/2020 - 21:35

#21

-NMi-

Offline

Зарегистрирован: 20.08.2018

Надо деда просить, чтобы пояснил.

Пт, 04/12/2020 - 21:42

#22

Komandir

Offline

Зарегистрирован: 18.08.2018

Вот тут видно:

Пт, 04/12/2020 - 22:02

#23

ЕвгенийП

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Зарегистрирован: 25.05.2015

Зафаворитил :-)

Пт, 04/12/2020 - 23:42

#24

Logik

Offline

Зарегистрирован: 05.08.2014

Komandir пишет:

В железе тестировал на OLED 128x32 SSD1306. Код для него ещё короче, так как не нужны функции i2c_restart и i2c_read.

192 кадра в секунду !!!

Опоздал ты с идеей на пяток лет. ))) Поищи, это ещё с Архатом и ещё кем-то тогда со всех сторон обгрызли идею. И юзаю так, даже прямо сейчас. И нету там 1МГц. Говориш 192 ФПС. Считаем192*512*9=884КГц Девять тактов на байт - потому что АСК.. Все верно, дето так и у нас получалось.

АСМ там не нужен совсем. Пиши просто на Си, соберется считай так же.

Теперь о плохом.

Жаль что ТС так и не понял как работает I2C )))) Уровень 1 на SDA контроллер не выводит никогда. Нужно просто отпустить шину, а к 1 ее подтягивают резюки. Их там вообще 2, сказанное относится и к SCL по большому счету, но мультимастер - экзотика.Отпустить шины - это на ввод настроить.

АСК контролировать обязательно! Как только перейдеш от примера на ssd1306, на пример, к примеру на 24c512 - поймеш зачем.

Но именно вот такую реализацию, без резюков подтяжки, без контроля АСК, но на Си и с нормальной задачей пинов ( ну просто их номером) я таки храню. Чтоб по быстряку ОЛЕД покинуть на любые ноги для отладки. Да и в проектах иногда подтяжки память влом ))) Пошарся по форуму, тут даже видео его работы лето валяется, там и осцилограф и ДПФ и диаграмки отрисовывает.

Пт, 04/12/2020 - 23:44

#25

wdrakula

Offline

Зарегистрирован: 15.03.2016

Logik пишет:

Поищи, это ещё с Архатом и ещё кем-то тогда со всех сторон обгрызли идею.

Нарочно жопой крутишь? Это мой код софт И2С был, его и трахали по разному. До Миллиона довести нельзя. Но если всё увести в ассемблер, конечно не так, как тут, то может быть получится. Если родная softI2C на arduino.cc очень грамотная. Которую можно ускорить, зная протокол (убрав проверки на "медленный слейв").

Пт, 04/12/2020 - 23:52

#26

Logik

Offline

Зарегистрирован: 05.08.2014

Явился не прошенный, ещё и с претензией, не понятно на что. У меня моя реализация. А что у тебя там с Ахатом общее - сами решайте, главное не на людях ;)

Сб, 05/12/2020 - 00:15

#27

Komandir

Offline

Зарегистрирован: 18.08.2018

Logik пишет:

Komandir пишет:

В железе тестировал на OLED 128x32 SSD1306. Код для него ещё короче, так как не нужны функции i2c_restart и i2c_read.

192 кадра в секунду !!!

АСМ там не нужен совсем. Пиши просто на Си, соберется считай так же.

Теперь о плохом.

Ну что тут сказать ...
Ты мальчик еще мал и глуп и не видал больших за...п !!!

Про скорость - скорость шины измеряется периодом следования сигналов на линии SCL !!!

Где ты тут нашел выставление 1 ? Тут ВЕЗДЕ подтяжка к нулю или отпускание !!! И на схеме R1 R2 для красоты что ли ???

Тут есть не только контроль ASK, но даже есть контроль удержания ведомым линии SCL в низком состоянии для паузы на обработку !!!

Разуй глаза ...

Сб, 05/12/2020 - 00:34

#28

Logik

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Вау! К нам спец по за..там пожаловал!

Ну раздвигайся, принимай первую. Если за 1 сек на SCL 884тысячи импульсов прошло, то какая частота на SCL?

Сб, 05/12/2020 - 00:55

#29

Komandir

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9 тактов SCL за 9 микросекунд - это какая частота ?

Аппаратный i2c:
на 100 КГц выдает 9 тактов SCL за 90 микросекунд
на 400 КГц выдает 9 тактов SCL за 22,5 микросекунды
следовательно:
на 1000 КГц 9 тактов SCL должны генерироваться именно за 9 микросекунд !!!

Сб, 05/12/2020 - 01:33

#30

wdrakula

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Logik пишет:

Спать уже ушел. С тилипона сложно... Логик! Шаббат шалом! Прочитай "Шма Исраэль" и ложись спать. Хорош тут лысого гонять на форумах. Не круто;)))

Сб, 05/12/2020 - 02:41

#31

Logik

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///
9 тактов SCL за 9 микросекунд - это какая частота ?/p>

Такс, отвечаем вопросом на вопрос.... Ну ясно, спец по за..пам должен быть обрезаным.

Про 9 мкс на 9 тактов. Ты видно таки решил что тут самый обрезаный ))) И пропустил что любые 9 тактов за 9 мксек в течении сеанса обмена. А не некоторые, избранные. Вот если сделаеш так и продемонстрируеш опытным путём, по ФПС экрана, что хотя бы в среднем 9мксек на 9 тактов - добро пожаловать. А пока наслаждайся за..пой.

Повторяю вопрос. Какая частота шины при измеренных 192 фПС? В мои годы студентов, не отвечающих на такой вопрос отправляли применять сапоги и шинель. У замдекана спецом комплект хранился. Ты пишеш командир...из таких похоже.

Сб, 05/12/2020 - 02:45

#32

Logik

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wdrakula пишет:

Logik пишет:

И тебе шалом, православный.

Та тут же лысый со знанием асма подвергался. Часто ль такое было!

Пс. Сам с планшета набирать замучался.

Сб, 05/12/2020 - 09:29

#33

Komandir

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Если обратиться к первоисточнику:

Сб, 05/12/2020 - 09:39

#34

Komandir

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Это генерирует мой код:

Сб, 05/12/2020 - 09:50

#35

Komandir

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А тупых преподавателей везде хватает ! У нас в МЭИ был один похожий ... оценивал код на вес бумаги, на которой его распечатывали.

Logik это не ты в МЭИ преподавал нам ???

С частотой SCL ты жидко обделался !!!

Перейдём ко второму вопросу..

В какой строке я выставил "1" в порту для SCL или SDA, а не отпустил линию (перевел её в состояние входа) ?

Сб, 05/12/2020 - 10:00

#36

ЕвгенийП

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Komandir, разворошили :-)

Говорили ж мудрые англичане: "Let sleeping dogs lie" :-)

Сб, 05/12/2020 - 10:08

#37

Komandir

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Вдогонку - аппаратная передача на 100 КГц:

Сб, 05/12/2020 - 10:11

#38

Komandir

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и аппаратная передача на 400 КГц:

Сб, 05/12/2020 - 10:13

#39

Komandir

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ЕвгенийП кто кого разбудил то ?

Сб, 05/12/2020 - 12:26

#40

-NMi-

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Уровень 1 на SDA контроллер не выводит никогда. Нужно просто отпустить шину, а к 1 ее подтягивают резюки. Их там вообще 2, сказанное относится и к SCL по большому счету, но мультимастер - экзотика.Отпустить шины - это на ввод настроить.

Ligik всё уже объяснил выше.

В таком случае нам понадобятся две команды, одна из них CBI х,у для прижатия шины к земле, вторая DDRх,у для перевода пина на вход/выход для "отпускания" шины, т.е. выставления лог. 1 на ней.

Сб, 05/12/2020 - 12:36

#41

Komandir

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-NMi- Ещё один знаток ассемблера AVR ? А как выглядит DDR x,y ? Раскройте мне глаза ?

Что па Вашему делают следующие команды, если SCLPORT=SDAPORT=PORTC=0x08 ?

1CBI SCLPORT-1,SCLPIN
2CBI SDAPORT-1,SDAPIN
3CBI SDAPORT,SDAPIN
4CBI SCLPORT,SCLPIN

Сб, 05/12/2020 - 12:50

#42

ua6em

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Komandir пишет:

-NMi- Ещё один знаток ассемблера AVR ? А как выглядит DDR x,y ? Раскройте мне глаза ?

Что па Вашему делают следующие команды, если SCLPORT=SDAPORT=PORTC=0x08 ?

1CBI SCLPORT-1,SCLPIN
2CBI SDAPORT-1,SDAPIN
3CBI SDAPORT,SDAPIN
4CBI SCLPORT,SCLPIN

смахивает на битву одного против трёх мушкетёров )))

Сб, 05/12/2020 - 13:11

#43

Komandir

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ua6em воспитателя и детсадовцев ...

Сб, 05/12/2020 - 13:17

#44

-NMi-

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Зачем так агрессировать? Просто мне не понятна одна вещь: для того, чтобы прижать пин к земле сколько нужно команд? Одна или две? Вот в чём вопрос..

Как по мне, нужно:

1 - сделать пин выходом

2 - сбросить бит в регистре пина, чтобы он вывел на пин "0"

И наоборот:

1 - сделать пин входом

2 - выставить бит пина в "1"

Или же просто манипулировать DDRх пинами без изменения битов регистра порта? Вот в чём вопрос...

Сб, 05/12/2020 - 14:12

#45

Komandir

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01CBI SCLPORT-1,SCLPIN    // Вывод SCL - вход
02CBI SDAPORT-1,SDAPIN    // Вывод SDA - вход
03CBI SDAPORT,SDAPIN      // Значение SDA=0. Дальше это значение не меняется НИ РАЗУ!!!
04CBI SCLPORT,SCLPIN      // Значение SCL=0. Дальше это значение не меняется НИ РАЗУ!!!
05// Это инициализация линий. После этого
06// Командой CBI SCLPORT-1,SCLPIN отпускается шина и получаем "1" от резистора подтяжки
07// Командой SBI SCLPORT-1,SCLPIN притягиваем шину к записанному "0" и получаем "0"
08// Командами SBIS / SBIC SCLPORT-2,SCLPIN можно проверить текущее состояние линии
09// Всё это вытекает из того что SCLPORT=PORC, а SCLPORT-1=DDRC и SCLPORT-2=PINC.
10// Это прописано в m328Pdef.inc

...

.equ PORTD = 0x0b

.equ DDRD = 0x0a

.equ PIND = 0x09

.equ PORTC = 0x08

.equ DDRC = 0x07

.equ PINC = 0x06

.equ PORTB = 0x05

.equ DDRB = 0x04

.equ PINB = 0x03

...

Сб, 05/12/2020 - 13:53

#46

ЕвгенийП

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Komandir пишет:

ЕвгенийП кто кого разбудил то ?

Ваша тема разбудила застарелый срач, который тихо дремал себе до поры :-)

Сб, 05/12/2020 - 13:54

#47

-NMi-

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Всё, вЪехал. Это просто для универсальности пользования сделано. Т.е. есть порт и есть пин в качестве констант или алиаса а дальше мы уже вычисляем те порты (регистры ввода-вывода), шо нужны нам.

))) с тилипона то не всё видно то... ))) вчерасЪ )))

Сб, 05/12/2020 - 14:03

#48

Komandir

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ЕвгенийП Вот Вы лично как считаете ? Частота SCL определяет скорость работы сдвигового регистра при выводе одного байта, или же надо учесть кто и какой лопатой загружает эти байты в сдвиговый регистр.

Сб, 05/12/2020 - 15:18

#49

Green

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Komandir, в i2c_read() всё красиво? Мне кажется на last никто не обращает внимания.

Сб, 05/12/2020 - 15:32

#50

Komandir

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Green В ассемблерном коде обратите внимание на стоки 148 и 150, в Сишном коде на строки 155 и 156.

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