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Как переназначить пины для энкодера?

3 ответа [Последнее сообщение]
Чт, 30/08/2018 - 00:22
10mills
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Зарегистрирован: 17.02.2018

Всем привет!

Нуждаюсь в помощи знающих людей. Нужно подключить энкодер, взял пример из библиотеки и все заработало, но там для выводов А2 и А3

#include <RotaryEncoder.h>

// Setup a RoraryEncoder for pins A2 and A3:
RotaryEncoder encoder(A2, A3);

void setup()
{
  Serial.begin(57600);
  Serial.println("SimplePollRotator example for the RotaryEncoder library.");

  // You may have to modify the next 2 lines if using other pins than A2 and A3
  PCICR |= (1 << PCIE1);    // This enables Pin Change Interrupt 1 that covers the Analog input pins or Port C.
  PCMSK1 |= (1 << PCINT10) | (1 << PCINT11);  // This enables the interrupt for pin 2 and 3 of Port C.
} // setup()

Вот с ними работает, но мне нужно чтоб DT - 13 и CLK - 11, я сделал так

PCICR |= (1 << PCIE1);
PCMSK1 |= (1 << PCINT5) | (1 << PCINT3);

Но ничего не заработало.

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Чт, 30/08/2018 - 01:03
#1
ЕвгенийП
ЕвгенийП аватар
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Зарегистрирован: 25.05.2015

А кто будет PCIE1 на PCIE0 и PCMSK1, на PCMSK0 менять?

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Чт, 30/08/2018 - 01:22
#2
10mills
Offline
Зарегистрирован: 17.02.2018

Поэтому и спрашиваю, потому что не знаю. Я же IDE-шник :( Если посоветуете какой материал не академического уровня- с удовольствием почитаю.

Спасибо за помощь, все заработало.

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Чт, 30/08/2018 - 13:19
#3
wdrakula
wdrakula аватар
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Зарегистрирован: 15.03.2016

Источник назывется "даташит", читайте с удовольствием!

===============================================

17.2.4.
Pin Change Interrupt Control Register
Name:  PCICR
Offset:  0x68
Reset:  0x00
Property: -
 
Bit
Access
Reset
7
6
5
4
3
2 1 0
PCIE2 PCIE1 PCIE0
R/W R/W R/W
0 0 0
Bit 2 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 2 is
enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding
interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins
are enabled individually by the PCMSK2 Register.
Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 1 is
enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt
of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are
enabled individually by the PCMSK1 Register.
Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 0 is
enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt
of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled
individually by the PCMSK0 Register.
Atmel ATmega328/P [DATASHEET]
Atmel-42735A-ATmega328/P_Datasheet_Complete-06/2016
9217.2.5.
Pin Change Interrupt Flag Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name:  PCIFR
Offset:  0x3B
Reset:  0x00
Property: When addressing as I/O Register: address offset is 0x1B
 
Bit
Access
Reset
7
6
5
4
3
2 1 0
PCIF2 PCIF1 PCIF0
R/W R/W R/W
0 0 0
Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 will be set. If the I-bit
in SREG and the PCIE2 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing
'1' to it.
Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[14:8] pin triggers an interrupt request, PCIF1 will be set. If the I-bit in
SREG and the PCIE1 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it.
Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 will be set. If the I-bit in
SREG and the PCIE0 bit in PCICR are set, the MCU will jump to the corresponding Interrupt Vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to
it.
Atmel ATmega328/P [DATASHEET]
Atmel-42735A-ATmega328/P_Datasheet_Complete-06/2016
9317.2.6.
Pin Change Mask Register 2
Name:  PCMSK2
Offset:  0x6D
Reset:  0x00
Property: -
 
Bit
Access
Reset
7 6 5 4 3 2 1 0
PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PCINT16, PCINT17, PCINT18, PCINT19, PCINT20, PCINT21, PCINT22,
PCINT23: Pin Change Enable Mask
Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[23:16] is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[23:16] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Atmel ATmega328/P [DATASHEET]
Atmel-42735A-ATmega328/P_Datasheet_Complete-06/2016
9417.2.7.
Pin Change Mask Register 1
Name:  PCMSK1
Offset:  0x6C
Reset:  0x00
Property: -
 
Bit
Access
Reset
7
6 5 4 3 2 1 0
PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8
R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6 – PCINT8, PCINT9, PCINT10, PCINT11, PCINT12, PCINT13, PCINT14: Pin
Change Enable Mask
Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[15:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[15:8] is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Atmel ATmega328/P [DATASHEET]
Atmel-42735A-ATmega328/P_Datasheet_Complete-06/2016
9517.2.8.
Pin Change Mask Register 0
Name:  PCMSK0
Offset:  0x6B
Reset:  0x00
Property: -
 
Bit
Access
Reset
7 6 5 4 3 2 1 0
PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
Bits 7:0 – PCINTn: Pin Change Enable Mask [n = 7:0]
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If
PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding
I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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