Прерывания и сторонняя функция. Энкодер. Научите как правильно.

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Сб, 20/03/2021 - 19:36

BOOM

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Зарегистрирован: 14.11.2018

Приветствую всех.

Для работы с механическим энкодером использую такой код (Энкодер подключен на лапы 2 и 3.):

01void setup() {
02 
03  PCICR |= (1 << PCIE2);                              // |
04  PCMSK2 |= (1 << PCINT18) | (1 << PCINT19);          // | Нужно для работы прерываний 
05  sei();                                              // |
06   
07  Serial.begin(9600);
08}
09 
10ISR(PCINT2_vect) {                   
11 
12  unsigned char result = r.process();  
13  if (result == DIR_CW)
14    set_frequency(1);
15  else if (result == DIR_CCW)
16    set_frequency(-1);
17}
18 
19void loop() {
20   
21}

Все прекрасно работает. При повороте энкодера в обе стороны вижу в serial как все четко отрабатывает.

Дальше я подключаю библиотеку si5351mcu.h ( https://github.com/pavelmc/Si5351mcu ) и изменяю код вот таким образом:

01void setup() {
02 
03  PCICR |= (1 << PCIE2);                              // |
04  PCMSK2 |= (1 << PCINT18) | (1 << PCINT19);          // | Нужно для работы прерываний
05  sei();                                              // |
06   
07  Serial.begin(9600);
08 
09  Si.init();
10  Si.correction(-1997700);
11  Si.setPower(CLK_0, SIOUT_8mA);
12  Si.setPower(CLK_1, SIOUT_8mA);
13  Si.setFreq(CLK_0, 1000000UL);
14  Si.setFreq(CLK_1, 465000UL);
15  Si.enable(CLK_0);
16  Si.enable(CLK_1);
17  Si.reset();
18   
19}
20 
21ISR(PCINT2_vect) {                   
22 
23  unsigned char result = r.process();  
24  if (result == DIR_CW)
25    set_frequency(1);
26  else if (result == DIR_CCW)
27    set_frequency(-1);
28 
29//  Si.setFreq(0, 2000000UL);
30}

Все работает, модуль на Si5351 генерирует колебания. Но до тех пор, пока я не раскомментирую строку "Si.setFreq(0, 2000000UL);".

Как только строка "Si.setFreq(0, 2000000UL);" раскомментирована реакция на вращение энкодера пропадает от слова совсем.

Содержимое функции Si.setFreq():

001void Si5351mcu::setFreq(uint8_t clk, uint32_t freq) {
002    uint8_t a, R = 1, pll_stride = 0, msyn_stride = 0;
003    uint32_t b, c, f, fvco, outdivider;
004    uint32_t MSx_P1, MSNx_P1, MSNx_P2, MSNx_P3;
005 
006    // Overclock option
007    #ifdef SI_OVERCLOCK
008        // user a overclock setting for the VCO, max value in my hardware
009        // was 1.05 to 1.1 GHz, as usual YMMV [See README.md for details]
010        outdivider = SI_OVERCLOCK / freq;
011    #else
012        // normal VCO from the datasheet and AN
013        // With 900 MHz beeing the maximum internal PLL-Frequency
014        outdivider = 900000000 / freq;
015    #endif
016 
017    // use additional Output divider ("R")
018    while (outdivider > 900) {
019        R = R * 2;
020        outdivider = outdivider / 2;
021    }
022 
023    // finds the even divider which delivers the intended Frequency
024    if (outdivider % 2) outdivider--;
025 
026    // Calculate the PLL-Frequency (given the even divider)
027    fvco = outdivider * R * freq;
028 
029    // Convert the Output Divider to the bit-setting required in register 44
030    switch (R) {
031        case 1:   R = 0; break;
032        case 2:   R = 16; break;
033        case 4:   R = 32; break;
034        case 8:   R = 48; break;
035        case 16:  R = 64; break;
036        case 32:  R = 80; break;
037        case 64:  R = 96; break;
038        case 128: R = 112; break;
039    }
040 
041    // we have now the integer part of the output msynth
042    // the b & c is fixed below
043     
044    MSx_P1 = 128 * outdivider - 512;
045 
046    // calc the a/b/c for the PLL Msynth
047    /***************************************************************************
048    * We will use integer only on the b/c relation, and will >> 5 (/32) both
049    * to fit it on the 1048 k limit of C and keep the relation
050    * the most accurate possible, this works fine with xtals from
051    * 24 to 28 Mhz.
052    *
053    * This will give errors of about +/- 2 Hz maximum
054    * as per my test and simulations in the worst case, well below the
055    * XTAl ppm error...
056    *
057    * This will free more than 1K of the final eeprom
058    *
059    ****************************************************************************/
060    a = fvco / int_xtal;
061    b = (fvco % int_xtal) >> 5;     // Integer part of the fraction
062                                    // scaled to match "c" limits
063    c = int_xtal >> 5;              // "c" scaled to match it's limits
064                                    // in the register
065 
066    // f is (128*b)/c to mimic the Floor(128*(b/c)) from the datasheet
067    f = (128 * b) / c;
068 
069    // build the registers to write
070    MSNx_P1 = 128 * a + f - 512;
071    MSNx_P2 = 128 * b - f * c;
072    MSNx_P3 = c;
073 
074    // PLLs and CLK# registers are allocated with a stride, we handle that with
075    // the stride var to make code smaller
076    if (clk > 0 ) pll_stride = 8;
077 
078    // HEX makes it easier to human read on bit shifts
079    uint8_t reg_bank_26[] = { 
080      (MSNx_P3 & 0xFF00) >> 8,          // Bits [15:8] of MSNx_P3 in register 26
081      MSNx_P3 & 0xFF,
082      (MSNx_P1 & 0x030000L) >> 16,
083      (MSNx_P1 & 0xFF00) >> 8,          // Bits [15:8]  of MSNx_P1 in register 29
084      MSNx_P1 & 0xFF,                   // Bits [7:0]  of MSNx_P1 in register 30
085      ((MSNx_P3 & 0x0F0000L) >> 12) | ((MSNx_P2 & 0x0F0000) >> 16), // Parts of MSNx_P3 and MSNx_P1
086      (MSNx_P2 & 0xFF00) >> 8,          // Bits [15:8]  of MSNx_P2 in register 32
087      MSNx_P2 & 0xFF                    // Bits [7:0]  of MSNx_P2 in register 33
088    };
089 
090    // We could do this here - but move it next to the reg_bank_42 write
091    // i2cWriteBurst(26 + pll_stride, reg_bank_26, sizeof(reg_bank_26));
092 
093    // Write the output divider msynth only if we need to, in this way we can
094    // speed up the frequency changes almost by half the time most of the time
095    // and the main goal is to avoid the nasty click noise on freq change
096    if (omsynth[clk] != outdivider || o_Rdiv[clk] != R ) {
097       
098        // CLK# registers are exactly 8 * clk# bytes stride from a base register.
099        msyn_stride = clk * 8;
100 
101        // keep track of the change
102        omsynth[clk] = (uint16_t) outdivider;
103        o_Rdiv[clk] = R;    // cache it now, before we OR mask up R for special divide by 4
104 
105        // See datasheet, special trick when MSx == 4
106        //    MSx_P1 is always 0 if outdivider == 4, from the above equations, so there is 
107        //    no need to set it to 0. ... MSx_P1 = 128 * outdivider - 512;
108        //  
109        //        See para 4.1.3 on the datasheet.
110        // 
111         
112        if ( outdivider == 4 ) {
113          R |= 0x0C;    // bit set OR mask for MSYNTH divide by 4, for reg 44 {3:2]
114        }
115         
116        // HEX makes it easier to human read on bit shifts
117        uint8_t reg_bank_42[] = { 
118          0,                         // Bits [15:8] of MS0_P3 (always 0) in register 42
119          1,                         // Bits [7:0]  of MS0_P3 (always 1) in register 43
120          ((MSx_P1 & 0x030000L ) >> 16) | R,  // Bits [17:16] of MSx_P1 in bits [1:0] and R in [7:4] | [3:2]
121          (MSx_P1 & 0xFF00) >> 8,    // Bits [15:8]  of MSx_P1 in register 45
122          MSx_P1 & 0xFF,             // Bits [7:0]  of MSx_P1 in register 46
123          0,                         // Bits [19:16] of MS0_P2 and MS0_P3 are always 0
124          0,                         // Bits [15:8]  of MS0_P2 are always 0
125          0                          // Bits [7:0]   of MS0_P2 are always 0
126        };
127         
128        // Get the two write bursts as close together as possible,
129        // to attempt to reduce any more click glitches.  This is   
130        // at the expense of only 24 increased bytes compilation size in AVR 328.
131        // Everything is already precalculated above, reducing any delay,  
132        // by not doing calculations between the burst writes.
133         
134        i2cWriteBurst(26 + pll_stride, reg_bank_26, sizeof(reg_bank_26));
135        i2cWriteBurst(42 + msyn_stride, reg_bank_42, sizeof(reg_bank_42));
136 
137        // 
138        // <a href="https://www.silabs.com/documents/public/application-notes/Si5350-Si5351%20FAQ.pdf" title="https://www.silabs.com/documents/public/application-notes/Si5350-Si5351%20FAQ.pdf" rel="nofollow">https://www.silabs.com/documents/public/application-notes/Si5350-Si5351%...</a>
139        // 
140        // 11.1 "The Int, R and N register values inside the Interpolative Dividers are updated 
141        //      when the LSB of R is written via I2C." - Q. does this mean reg 44 or 49 (misprint ?) ???
142        //
143        // 10.1 "All outputs are within +/- 500ps of one another at power up (if pre-programmed) 
144        //      or if PLLA and PLLB are reset simultaneously via register 177."
145        // 
146        // 17.1 "The PLL can track any abrupt input frequency changes of 3–4% without losing 
147        //      lock to it. Any input frequency changes greater than this amount will not 
148        //      necessarily track from the input to the output 
149         
150        // must reset the so called "PLL", in fact the output msynth
151        reset();
152 
153    }
154    else {
155          i2cWriteBurst(26 + pll_stride, reg_bank_26, sizeof(reg_bank_26));
156    }
157 
158}

Все функции бибилиотеки (для ленивых :-) ):

001/*
002 * si5351mcu - Si5351 library for Arduino MCU tuned for size and click-less
003 *
004 * Copyright (C) 2017 Pavel Milanes <pavelmc@gmail.com>
005 *
006 * Many chunk of codes are derived-from/copied from other libs
007 * all GNU GPL licenced:
008 *  - Linux Kernel (<a href="http://www.kernel.org" title="www.kernel.org" rel="nofollow">www.kernel.org</a>)
009 *  - Hans Summers libs and demo code (qrp-labs.com)
010 *  - Etherkit (NT7S) Si5351 libs on github
011 *  - DK7IH example.
012 *  - Jerry Gaffke integer routines for the bitx20 group
013 *
014 * This program is free software: you can redistribute it and/or modify
015 * it under the terms of the GNU General Public License as published by
016 * the Free Software Foundation, either version 3 of the License, or
017 * (at your option) any later version.
018 *
019 * This program is distributed in the hope that it will be useful,
020 * but WITHOUT ANY WARRANTY; without even the implied warranty of
021 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
022 * GNU General Public License for more details.
023 *
024 * You should have received a copy of the GNU General Public License
025 * along with this program.  If not, see <<a href="http://www.gnu.org/licenses/" rel="nofollow">http://www.gnu.org/licenses/</a>>.
026 */
027 
028#include "Arduino.h"
029#include "si5351mcu.h"
030 
031// wire library loading, if not defined
032#ifndef WIRE_H
033    #include "Wire.h"
034#endif
035 
036/*****************************************************************************
037 * This is the default init procedure, it set the Si5351 with this params:
038 * XTAL 27.000 Mhz
039 *****************************************************************************/
040 void Si5351mcu::init(void) {
041    // init with the default freq
042    init(int_xtal);
043}
044 
045 
046/*****************************************************************************
047 * This is the custom init procedure, it's used to pass a custom xtal
048 * and has the duty of init the I2C protocol handshake
049 *****************************************************************************/
050 void Si5351mcu::init(uint32_t nxtal) {
051    // set the new base xtal freq
052    base_xtal = int_xtal = nxtal;
053 
054    // start I2C (wire) procedures
055    Wire.begin();
056 
057    // power off all the outputs
058    off();
059}
060 
061 
062/*****************************************************************************
063 * This function set the freq of the corresponding clock.
064 *
065 * In my tests my Si5351 can work between 7,8 Khz and ~225 Mhz [~250 MHz with
066 * overclocking] as usual YMMV
067 *
068 * Click noise:
069 * - The lib has a reset programmed [aka: click noise] every time it needs to
070 *   change the output divider of a particular MSynth, if you move in big steps
071 *   this can lead to an increased rate of click noise per tunning step.
072 * - If you move at a pace of a few Hz each time the output divider will
073 *   change at a low rate, hence less click noise per tunning step.
074 * - The output divider moves [change] faster at high frequencies, so at HF the
075 *   clikc noise is at the real minimum possible.
076 *
077 * [See the README.md file for other details]
078 ****************************************************************************/
079void Si5351mcu::setFreq(uint8_t clk, uint32_t freq) {
080    uint8_t a, R = 1, pll_stride = 0, msyn_stride = 0;
081    uint32_t b, c, f, fvco, outdivider;
082    uint32_t MSx_P1, MSNx_P1, MSNx_P2, MSNx_P3;
083 
084    // Overclock option
085    #ifdef SI_OVERCLOCK
086        // user a overclock setting for the VCO, max value in my hardware
087        // was 1.05 to 1.1 GHz, as usual YMMV [See README.md for details]
088        outdivider = SI_OVERCLOCK / freq;
089    #else
090        // normal VCO from the datasheet and AN
091        // With 900 MHz beeing the maximum internal PLL-Frequency
092        outdivider = 900000000 / freq;
093    #endif
094 
095    // use additional Output divider ("R")
096    while (outdivider > 900) {
097        R = R * 2;
098        outdivider = outdivider / 2;
099    }
100 
101    // finds the even divider which delivers the intended Frequency
102    if (outdivider % 2) outdivider--;
103 
104    // Calculate the PLL-Frequency (given the even divider)
105    fvco = outdivider * R * freq;
106 
107    // Convert the Output Divider to the bit-setting required in register 44
108    switch (R) {
109        case 1:   R = 0; break;
110        case 2:   R = 16; break;
111        case 4:   R = 32; break;
112        case 8:   R = 48; break;
113        case 16:  R = 64; break;
114        case 32:  R = 80; break;
115        case 64:  R = 96; break;
116        case 128: R = 112; break;
117    }
118 
119    // we have now the integer part of the output msynth
120    // the b & c is fixed below
121     
122    MSx_P1 = 128 * outdivider - 512;
123 
124    // calc the a/b/c for the PLL Msynth
125    /***************************************************************************
126    * We will use integer only on the b/c relation, and will >> 5 (/32) both
127    * to fit it on the 1048 k limit of C and keep the relation
128    * the most accurate possible, this works fine with xtals from
129    * 24 to 28 Mhz.
130    *
131    * This will give errors of about +/- 2 Hz maximum
132    * as per my test and simulations in the worst case, well below the
133    * XTAl ppm error...
134    *
135    * This will free more than 1K of the final eeprom
136    *
137    ****************************************************************************/
138    a = fvco / int_xtal;
139    b = (fvco % int_xtal) >> 5;     // Integer part of the fraction
140                                    // scaled to match "c" limits
141    c = int_xtal >> 5;              // "c" scaled to match it's limits
142                                    // in the register
143 
144    // f is (128*b)/c to mimic the Floor(128*(b/c)) from the datasheet
145    f = (128 * b) / c;
146 
147    // build the registers to write
148    MSNx_P1 = 128 * a + f - 512;
149    MSNx_P2 = 128 * b - f * c;
150    MSNx_P3 = c;
151 
152    // PLLs and CLK# registers are allocated with a stride, we handle that with
153    // the stride var to make code smaller
154    if (clk > 0 ) pll_stride = 8;
155 
156    // HEX makes it easier to human read on bit shifts
157    uint8_t reg_bank_26[] = { 
158      (MSNx_P3 & 0xFF00) >> 8,          // Bits [15:8] of MSNx_P3 in register 26
159      MSNx_P3 & 0xFF,
160      (MSNx_P1 & 0x030000L) >> 16,
161      (MSNx_P1 & 0xFF00) >> 8,          // Bits [15:8]  of MSNx_P1 in register 29
162      MSNx_P1 & 0xFF,                   // Bits [7:0]  of MSNx_P1 in register 30
163      ((MSNx_P3 & 0x0F0000L) >> 12) | ((MSNx_P2 & 0x0F0000) >> 16), // Parts of MSNx_P3 and MSNx_P1
164      (MSNx_P2 & 0xFF00) >> 8,          // Bits [15:8]  of MSNx_P2 in register 32
165      MSNx_P2 & 0xFF                    // Bits [7:0]  of MSNx_P2 in register 33
166    };
167 
168    // We could do this here - but move it next to the reg_bank_42 write
169    // i2cWriteBurst(26 + pll_stride, reg_bank_26, sizeof(reg_bank_26));
170 
171    // Write the output divider msynth only if we need to, in this way we can
172    // speed up the frequency changes almost by half the time most of the time
173    // and the main goal is to avoid the nasty click noise on freq change
174    if (omsynth[clk] != outdivider || o_Rdiv[clk] != R ) {
175       
176        // CLK# registers are exactly 8 * clk# bytes stride from a base register.
177        msyn_stride = clk * 8;
178 
179        // keep track of the change
180        omsynth[clk] = (uint16_t) outdivider;
181        o_Rdiv[clk] = R;    // cache it now, before we OR mask up R for special divide by 4
182 
183        // See datasheet, special trick when MSx == 4
184        //    MSx_P1 is always 0 if outdivider == 4, from the above equations, so there is 
185        //    no need to set it to 0. ... MSx_P1 = 128 * outdivider - 512;
186        //  
187        //        See para 4.1.3 on the datasheet.
188        // 
189         
190        if ( outdivider == 4 ) {
191          R |= 0x0C;    // bit set OR mask for MSYNTH divide by 4, for reg 44 {3:2]
192        }
193         
194        // HEX makes it easier to human read on bit shifts
195        uint8_t reg_bank_42[] = { 
196          0,                         // Bits [15:8] of MS0_P3 (always 0) in register 42
197          1,                         // Bits [7:0]  of MS0_P3 (always 1) in register 43
198          ((MSx_P1 & 0x030000L ) >> 16) | R,  // Bits [17:16] of MSx_P1 in bits [1:0] and R in [7:4] | [3:2]
199          (MSx_P1 & 0xFF00) >> 8,    // Bits [15:8]  of MSx_P1 in register 45
200          MSx_P1 & 0xFF,             // Bits [7:0]  of MSx_P1 in register 46
201          0,                         // Bits [19:16] of MS0_P2 and MS0_P3 are always 0
202          0,                         // Bits [15:8]  of MS0_P2 are always 0
203          0                          // Bits [7:0]   of MS0_P2 are always 0
204        };
205         
206        // Get the two write bursts as close together as possible,
207        // to attempt to reduce any more click glitches.  This is   
208        // at the expense of only 24 increased bytes compilation size in AVR 328.
209        // Everything is already precalculated above, reducing any delay,  
210        // by not doing calculations between the burst writes.
211         
212        i2cWriteBurst(26 + pll_stride, reg_bank_26, sizeof(reg_bank_26));
213        i2cWriteBurst(42 + msyn_stride, reg_bank_42, sizeof(reg_bank_42));
214 
215        // 
216        // <a href="https://www.silabs.com/documents/public/application-notes/Si5350-Si5351%20FAQ.pdf" title="https://www.silabs.com/documents/public/application-notes/Si5350-Si5351%20FAQ.pdf" rel="nofollow">https://www.silabs.com/documents/public/application-notes/Si5350-Si5351%...</a>
217        // 
218        // 11.1 "The Int, R and N register values inside the Interpolative Dividers are updated 
219        //      when the LSB of R is written via I2C." - Q. does this mean reg 44 or 49 (misprint ?) ???
220        //
221        // 10.1 "All outputs are within +/- 500ps of one another at power up (if pre-programmed) 
222        //      or if PLLA and PLLB are reset simultaneously via register 177."
223        // 
224        // 17.1 "The PLL can track any abrupt input frequency changes of 3–4% without losing 
225        //      lock to it. Any input frequency changes greater than this amount will not 
226        //      necessarily track from the input to the output 
227         
228        // must reset the so called "PLL", in fact the output msynth
229        reset();
230 
231    }
232    else {
233          i2cWriteBurst(26 + pll_stride, reg_bank_26, sizeof(reg_bank_26));
234    }
235 
236}
237 
238 
239/*****************************************************************************
240 * Reset of the PLLs and multisynths output enable
241 *
242 * This must be called to soft reset the PLLs and cycle the output of the
243 * multisynths: this is the "click" noise source in the RF spectrum.
244 *
245 * So it must be avoided at all costs, so this lib just call it at the
246 * initialization of the PLLs and when a correction is applied
247 *
248 * If you are concerned with accuracy you can implement a reset every
249 * other Mhz to be sure it get exactly on spot.
250 ****************************************************************************/
251void Si5351mcu::reset(void) {
252    // This soft-resets PLL A & B (32 + 128) in just one step
253    i2cWrite(177, 0xA0);
254}
255 
256 
257/*****************************************************************************
258 * Function to disable all outputs
259 *
260 * The PLL are kept running, just the m-synths are powered off.
261 *
262 * This allows to keep the chip warm and exactly on freq the next time you
263 * enable an output.
264 ****************************************************************************/
265void Si5351mcu::off(void) {
266    // This disable all the CLK outputs
267    for (byte i=0; i < SICHANNELS; i++) {
268      disable(i);
269    }
270}
271 
272 
273/*****************************************************************************
274 * Function to set the correction in Hz over the Si5351 XTAL.
275 *
276 * This will call a reset of the PLLs and multi-synths so it will produce a
277 * click every time it's called
278 ****************************************************************************/
279void Si5351mcu::correction(int32_t diff) {
280    // apply some corrections to the xtal
281    int_xtal = base_xtal + diff;
282 
283    // reset the PLLs to apply the correction
284    reset();
285}
286 
287 
288/*****************************************************************************
289 * This function enables the selected output
290 *
291 * Beware: ZERO is clock output enabled, in register 16+CLK
292 *****************************************************************************/
293void Si5351mcu::enable(uint8_t clk) {
294    // var to handle the mask of the registers value
295    uint8_t m = SICLK0_R;
296     
297    if (clk > 0) {
298      m = SICLK12_R;
299    }
300 
301    // write the register value
302    i2cWrite(16 + clk, m + clkpower[clk]);
303 
304    // 1 & 2 are mutually exclusive
305    if (clk == 1) disable(2);
306    if (clk == 2) disable(1);
307 
308    // update the status of the clk
309    clkOn[clk] = 1;
310}
311 
312 
313/*****************************************************************************
314 * This function disables the selected output
315 *
316 * Beware: ONE is clock output disabled, in register 16+CLK
317 * *****************************************************************************/
318void Si5351mcu::disable(uint8_t clk) {
319    // send
320    i2cWrite(16 + clk, 0x80);
321 
322    // update the status of the clk
323    clkOn[clk] = 0;
324}
325 
326 
327/****************************************************************************
328 * Set the power output for each output independently
329 ***************************************************************************/
330void Si5351mcu::setPower(uint8_t clk, uint8_t power) {
331    // set the power to the correct var
332    clkpower[clk] = power;
333 
334    // now enable the output to get it applied
335    enable(clk);
336}
337 
338/****************************************************************************
339 * method to send multi-byte burst register data.
340 ***************************************************************************/
341uint8_t Si5351mcu::i2cWriteBurst( const uint8_t start_register, 
342                                const uint8_t *data, 
343                                const uint8_t numbytes) {
344 
345    // This method saves the massive overhead of having to keep opening
346    // and closing the I2C bus for consecutive register writes.  It 
347    // also saves numbytes - 1 writes for register address selection.
348    Wire.beginTransmission(SIADDR);
349 
350    Wire.write(start_register);
351    Wire.write(data, numbytes);
352    // All of the bytes queued up in the above write() calls are buffered
353    // up and will be sent to the slave in one "burst", on the call to
354    // endTransmission().  This also sends the I2C STOP to the Slave.
355    return Wire.endTransmission();
356    // returns non zero on error
357}
358 
359/****************************************************************************
360 * function to send the register data to the Si5351, arduino way.
361 ***************************************************************************/
362void Si5351mcu::i2cWrite( const uint8_t regist, const uint8_t value) {
363    // Using the "burst" method instead of 
364    // doing it longhand saves a few bytes
365    i2cWriteBurst( regist, &value, 1);
366         
367}
368 
369/****************************************************************************
370 * Read i2C register, returns -1 on error or timeout
371 ***************************************************************************/
372int16_t  Si5351mcu::i2cRead( const uint8_t regist ) {
373    int value;
374 
375    Wire.beginTransmission(SIADDR);
376    Wire.write(regist);
377    Wire.endTransmission();
378     
379    Wire.requestFrom(SIADDR, 1);
380    if ( Wire.available() ) {
381      value = Wire.read();
382    }
383    else {
384      value = -1;   // "EOF" in C
385    }
386 
387    return value;
388}

Пол дня сегодня бьюсь и не могу сообразить. Как это все связано с прерываниями?

Прошу помощи более опытных специалистов.

Сб, 20/03/2021 - 20:41

andriano

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Зарегистрирован: 20.06.2015

Для начала я бы вынес функции из прерывания в loop(). А в прерывании сделал бы только установку флагов.

Сб, 20/03/2021 - 21:07

Green

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Зарегистрирован: 01.10.2015

Ну, вероятно, Si.setFreq(0, 2000000UL); слишком долго находится в прерывании, либо не корректно работает в прерывании. Вообще зачем она там? Нужно стремиться что бы функций в прерывания не было вообще!

Сб, 20/03/2021 - 21:25

BOOM

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Зарегистрирован: 14.11.2018

Большое спасибо за ответы. Сейчас попробовал выкинуть функции из прерывания и использовать флаг - все замечательно заработало.
Огромное спасибо ответившим! Век живи - век учись!... :-)

Пнд, 22/03/2021 - 22:16

BOOM

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Зарегистрирован: 14.11.2018

Я знаю, что есть специализированная тема по si5351 (если же нужно - перенесите в нее, я с "наскока" не нашел её).

Но спросить хочется. Я не сильно разбираюсь в английском языке, тем более в даташитах на мкросхемы (хотя хочетя, но видно не вышел "телом" ))) ). Но как я понял, DDS микросхема si5351 НЕ может генерировать нужной формы сигнал. Треугольник, пилу, обратную пилу, синусойду. Я использовал несколько бибилиотек, получил в итоге такие результаты: Примерно с 23-24МГц более менее нормальная синусойда, до этой частоты корявый "прямоугольник".

Я правильно понимаю, что на si5351 (за её цену) только так и возможно в "чистом виде"?

Заранее благодарю за ответы по моему вопросу.

Втр, 23/03/2021 - 07:09

dimax

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Зарегистрирован: 25.12.2013

BOOM пишет:

как я понял, DDS микросхема si5351 НЕ может генерировать нужной формы сигнал.

Да, и поэтому Si5351 называется генератор тактовых частот. А, например ad9833, которые это умеет называется генератор сигналов.

BOOM пишет:

Примерно с 23-24МГц более менее нормальная синусойда, до этой частоты корявый "прямоугольник".

Это зависит от того как подключить нагрузку, и от средства измерения. Вы нагрузили выход током, указанном в даташите? Ну и что б видеть "прямые углы" у меандра осциллограф должен иметь полосу пропускания и частоту дискретизации на несколько порядков выше измеряемой частоты.

Втр, 23/03/2021 - 08:49

BOOM

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Зарегистрирован: 14.11.2018

Большое спасибо за пояснения.

У меня не дорогой осциллограф на 100МГц (DSO5102P), но, судя по тому, как стремительно (после ~70МГц) начинает снижаться амплитуда сигнала, вносят свои "коррективы" еще и щупы, тупо "не справляются". А отдельно щуп на 1ГГц не дёшев (если брать хороший). Да и мне редко такие частоты высокие нужны.

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